FW82801EB Intel, FW82801EB Datasheet - Page 553

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

15.2.7
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
x_CR—Control Register
(Audio—D31:F5)
I/O Address:
Default Value:
Lockable:
Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit read from
the address offset 08h. Software can also read this register individually by doing a single, 8-bit read
to offset 0Bh. Reads across DWord boundaries are not supported.
7:5
Bit
4
3
2
1
0
Reserved.
Interrupt on Completion Enable (IOCE) — R/W. This bit controls whether or not an interrupt
occurs when a buffer completes with the IOC bit set in its descriptor.
0 = Disable. Interrupt will not occur.
1 = Enable
FIFO Error Interrupt Enable (FEIE) — R/W. This bit controls whether the occurrence of a FIFO
error will cause an interrupt or not.
0 = Disable. Bit 4 in the Status Register will be set, but the interrupt will not occur.
1 = Enable. Interrupt will occur.
Last Valid Buffer Interrupt Enable (LVBIE) — R/W. This bit controls whether the completion of the
last valid buffer will cause an interrupt or not.
0 = Disable. Bit 2 in the Status register will still be set, but the interrupt will not occur.
1 = Enable
Reset Registers (RR) — R/W (special).
0 = Removes reset condition.
1 = Contents of all Bus master related registers to be reset, except the interrupt enable bits (bit
Run/Pause Bus Master (RPBM) — R/W.
0 = Pause bus master operation. This results in all state information being retained (i.e., master
1 = Run. Bus master operation starts.
4,3,2 of this register). Software needs to set this bit but need not clear it since the bit is self
clearing. This bit must be set only when the Run/Pause bit is cleared. Setting it when the Run
bit is set will cause undefined consequences.
mode operation can be stopped and then resumed).
NABMBAR + 0Bh (PICR),
NABMBAR + 1Bh (POCR),
NABMBAR + 2Bh (MCCR)
MBBAR + 4Bh (MC2CR)
MBBAR + 5Bh (PI2CR)
MBBAR + 6Bh (SPCR)
00h
No
AC ’97 Audio Controller Registers (D31:F5)
Description
Attribute:
Size:
Power Well:
R/W, R/W (special)
8 bits
Core
553