FW82801EB Intel, FW82801EB Datasheet - Page 498

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

EHCI Controller Registers (D29:F7)
13.2.4
498
HCCPARAMS—Host Controller Capability Parameters
Register
Offset:
Default Value:
31:16
15:8
Bit
7:4
3
2
1
0
Reserved
EHCI Extended Capabilities Pointer (EECP) — RO. This field is hardwired to 68h, indicating that the
EHCI capabilities list exists and begins at offset 68h in the PCI configuration space.
Isochronous Scheduling Threshold — RO. This field indicates, relative to the current position of the
executing host controller, where software can reliably update the isochronous schedule. When bit 7
is 0, the value of the least significant 3 bits indicates the number of micro-frames a host controller
hold a set of isochronous data structures (one or more) before flushing the state. When bit 7 is a 1,
then host software assumes the host controller may cache an isochronous data structure for an
entire frame. Refer to the Enhanced Host Controller Interface Specification for Universal Serial Bus,
Revision 1.0 for details on how software uses this information for scheduling isochronous transfers.
This field is hardwired to 7h.
Reserved. These bits are reserved and should be set to 0.
Asynchronous Schedule Park Capability — RO. This bit is hardwired to 0 indicating that the Host
Controller does not support this optional feature
Programmable Frame List Flag — RO.
0 = System software must use a frame list length of 1024 elements with this host controller. The
1 = System software can specify and use a smaller frame list and configure the host controller via
64-bit Addressing Capability — RO. This field documents the addressing range capability of this
implementation. The value of this field determines whether software should use the 32-bit or 64-bit
data structures. Values for this field have the following interpretation:
0 = Data structures using 32-bit address memory pointers
1 = Data structures using 64-bit address memory pointers
This bit is hardwired to 1.
NOTE: Intel
USB2.0_CMD register Frame List Size field is a read-only register and must be set to 0.
the USB2.0_CMD register Frame List Size field. The frame list must always be aligned on a 4K
page boundary. This requirement ensures that the frame list is always physically contiguous.
08
00006871h
®
–
ICH5 only implements 44 bits of addressing. Bits 63:44 will always be 0.
0Bh
Description
Intel
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RO
32 bits