FW82801EB Intel, FW82801EB Datasheet - Page 163

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.13.11.5
5.13.12
Intel
®
Table 72. Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
Controlling Leakage and Power Consumption
Clock Generators
during Low-Power States
To control leakage in the system, various signals tri-state or go low during some low-power states.
General principles:
Based on the above principles, the following measures are taken:
The clock generator is expected to provide the frequencies shown in
AC_BIT_CLK
•
•
•
•
LAN_CLK
Domain
CLK100
PCICLK
CLK66
CLK48
CLK14
All signals going to powered down planes (either internally or externally) must be either
tri-stated or driven low.
Signals with pull-up resistors should not be low during low-power states. This is to avoid the
power consumed in the pull-up resistor.
Buses should be halted (and held) in a known state to avoid a floating input (perhaps to some
other device). Floating inputs can cause extra power consumption.
During S3 (STR), all signals attached to powered down planes are tri-stated or driven low.
Clock
®
ICH5 Clock Inputs
14.318 MHz
12.288 MHz
Frequency
Differential
100 MHz
66 MHz
33 MHz
48 MHz
50 MHz
0.8 to
Main Clock
Main Clock
Main Clock
Main Clock
Main Clock
Generator
Generator
Generator
Generator
Generator
Connect
Source
AC ’97
Codec
LAN
Used by SATA controller. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
Should be running in all Cx states. Stopped in S3 ~ S5 based
on SLP_S3# assertion.
Free-running PCI Clock to ICH5. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
Used by USB controllers. Stopped in S3 ~ S5 based on
SLP_S3# assertion.
Used by ACPI timers. Stopped in S3 ~ S5 based on SLP_S3#
assertion.
AC-link. Control policy is determined by the clock source.
LAN Connect link. Control policy is determined by the clock
source.
Usage
Table
Functional Description
72.
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