FW82801EB Intel, FW82801EB Datasheet - Page 396

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FW82801EB

Manufacturer Part Number
FW82801EB
Description
Manufacturer
Intel
Datasheet

Specifications of FW82801EB

Lead Free Status / RoHS Status
Not Compliant

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LPC Interface Bridge Registers (D31:F0)
9.10.8
396
SMI_EN—SMI Control and Enable Register
I/O Address:
Default Value:
Lockable:
Power Well:
31:19
16:15
10:8
Bit
18
17
14
13
12
11
7
6
5
4
Reserved
INTEL_USB2_EN — R/W.
0 = Disable
1 = Enables Intel-Specific USB2 SMI logic to cause SMI#.
LEGACY_USB2_EN — R/W.
0 = Disable
1 = Enables legacy USB2 logic to cause SMI#.
Reserved
PERIODIC_EN — R/W.
0 = Disable
1 = Enables the Intel
TCO_EN — R/W.
0 = Disables TCO logic generating an SMI#. Note that if the NMI2SMI_EN bit is set, SMIs that are
1 = Enables the TCO logic to generate SMI#.
NOTE: This bit cannot be written once the TCO_LOCK bit is set.
Reserved
MCSMI_ENMicrocontroller SMI Enable (MCSMI_EN) — R/W.
0 = Disable
1 = Enables ICH5 to trap accesses to the microcontroller range (62h or 66h) and generate an
Reserved
BIOS Release (BIOS_RLS) — WO.
0 = This bit will always return 0 on reads. Writes of 0 to this bit have no effect.
1 = Enables the generation of an SCI interrupt for ACPI software when a 1 is written to this bit
Software SMI# Timer Enable (SWSMI_TMR_EN) — R/W.
0 = Disable. Clearing the SWSMI_TMR_EN bit before the timer expires will reset the timer and the
1 = Starts Software SMI# Timer. When the SWSMI timer expires (the timeout period depends upon
APMC_EN — R/W.
0 = Disable. Writes to the APM_CNT register will not cause an SMI#.
1 = Enables writes to the APM_CNT register to cause an SMI#.
SLP_SMI_EN — R/W.
0 = Disables the generation of SMI# on SLP_EN. Note that this bit must be 0 before the software
1 = A write of 1 to the SLP_EN bit (bit 13 in PM1_CNT register) will generate an SMI#, and the
SMI_STS register.
caused by re-routed NMIs will not be gated by the TCO_EN bit. Even if the TCO_EN bit is 0,
NMIs will still be routed to cause SMIs.
SMI#. Note that “trapped’ cycles will be claimed by the ICH5 on PCI, but not forwarded to LPC.
position by BIOS software.
SMI# will not be generated.
the SWSMI_RATE_SEL bit setting), SWSMI_TMR_STS is set and an SMI# is generated.
SWSMI_TMR_EN stays set until cleared by software.
attempts to transition the system into a sleep state by writing a 1 to the SLP_EN bit.
system will not transition to the sleep state based on that write to the SLP_EN bit.
PMBASE + 30h
0000h
No
Core
®
ICH5 to generate an SMI# when the PERIODIC_STS bit is set in the
Intel
Description
Attribute:
Size:
Usage:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W, R/W (special), WO
32 bit
ACPI or Legacy

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