FW82801EB Intel, FW82801EB Datasheet - Page 164

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.13.13
5.13.13.1
5.14
164
Note: Voltage ID from the processor can be read via GPI signals.
APM Power Management
Legacy Power Management Theory of Operation
Instead of relying on ACPI software, legacy power management uses BIOS and various hardware
mechanisms. The scheme relies on the concept of detecting when individual subsystems are idle,
detecting when the whole system is idle, and detecting when accesses are attempted to idle
subsystems.
However, the OS is assumed to be at least APM enabled. Without APM calls, there is no quick way
to know when the system is idle between keystrokes. The ICH5 does not support burst modes.
The ICH5 has a timer that, when enabled by the 1MIN_EN bit in the SMI Control and Enable
register, generates an SMI# once per minute. The SMI handler can check for system activity by
reading the DEVACT_STS register. If none of the system bits are set, the SMI handler can
increment a software counter. When the counter reaches a sufficient number of consecutive
minutes with no activity, the SMI handler can then put the system into a lower power state.
If there is activity, various bits in the DEVACT_STS register will be set. Software clears the bits by
writing a 1 to the bit position.
The DEVACT_STS register allows for monitoring various internal devices, or Super I/O devices
(SP, PP, FDC) on LPC or PCI, keyboard controller accesses, or audio functions on LPC or PCI.
Other PCI activity can be monitored by checking the PCI interrupts.
System Management (D31:F0)
The ICH5 provides various functions to make a system easier to manage and to lower the Total
Cost of Ownership (TCO) of the system. In addition, ICH5 provides integrated ASF Management
support. Features and functions can be augmented via external A/D converters and GPIO, as well
as an external microcontroller.
The following features and functions are supported by the ICH5:
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Processor present detection
Various Error detection (such as ECC Errors) Indicated by host controller
Intruder Detect input
Detection of bad flash BIOS programming
Ability to hide a PCI device
Integrated ASF Management support
— Detects if processor fails to fetch the first instruction after reset
— Can generate SMI#, SCI, SERR, NMI, or TCO interrupt
— Can generate TCO interrupt or SMI# when the system cover is removed
— INTRUDER# allowed to go active in any power state, including G3
— Detects if data on first read is FFh (indicates unprogrammed flash BIOS)
— Allows software to hide a PCI device in terms of configuration space through the use of a
device hide register (See
Section
8.1.26)
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet