FW82801EB Intel, FW82801EB Datasheet - Page 90

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.2.2.2
90
Bus Master Operation
As a PCI Bus Master, the ICH5 integrated LAN controller initiates memory cycles to fetch data for
transmission or deposit received data and for accessing the memory resident control structures. The
LAN controller performs zero wait-state burst read and write cycles to the host main memory. For
bus master cycles, the LAN controller is the initiator and the host main memory (or the PCI host
bridge, depending on the configuration of the system) is the target.
The processor provides the LAN controller with action commands and pointers to the data buffers
that reside in host main memory. The LAN controller independently manages these structures and
initiates burst memory cycles to transfer data to and from them. The LAN controller uses the
Memory Read Multiple (MR Multiple) command for burst accesses to data buffers and the
Memory Read Line (MR Line) command for burst accesses to control structures. For all write
accesses to the control structure, the LAN controller uses the Memory Write (MW) command. For
write accesses to data structure, the LAN controller may use either the Memory Write or Memory
Write and Invalidate (MWI) commands.
Read Accesses: The LAN controller performs block transfers from host system memory in order
to perform frame transmission on the serial link. In this case, the LAN controller initiates zero
wait-state memory read burst cycles for these accesses. The length of a burst is bounded by the
system and the LAN controller’s internal FIFO. The length of a read burst may also be bounded by
the value of the Transmit DMA Maximum Byte Count in the Configure command. The Transmit
DMA Maximum Byte Count value indicates the maximum number of transmit DMA PCI cycles
that will be completed after an LAN controller internal arbitration.
The LAN controller, as the initiator, drives the address lines AD[31:0], the command and byte
enable lines C/BE[3:0]# and the control lines IRDY# and FRAME#. The LAN controller asserts
IRDY# to support zero wait-state burst cycles. The target signals the LAN controller that valid data
is ready to be read by asserting the TRDY# signal.
Write Accesses: The LAN controller performs block transfers to host system memory during
frame reception. In this case, the LAN controller initiates memory write burst cycles to deposit the
data, usually without wait-states. The length of a burst is bounded by the system and the LAN
controller’s internal FIFO threshold. The length of a write burst may also be bounded by the value
of the Receive DMA Maximum Byte Count in the Configure command. The Receive DMA
Maximum Byte Count value indicates the maximum number of receive DMA PCI transfers that
will be completed before the LAN controller internal arbitration.
The LAN controller, as the initiator, drives the address lines AD[31:0], the command and byte
enable lines C/BE[3:0]# and the control lines IRDY# and FRAME#. The LAN controller asserts
IRDY# to support zero wait-state burst cycles. The LAN controller also drives valid data on
AD[31:0] lines during each data phase (from the first clock and on). The target controls the length
and signals completion of a data phase by deassertion and assertion of TRDY#.
Intel
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82801EB ICH5 / 82801ER ICH5R Datasheet