FW82801EB Intel, FW82801EB Datasheet - Page 323

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.1.11
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
ACPI_CNTL—ACPI Control Register
(LPC I/F — D31:F0)
Offset Address:
Default Value:
Lockable:
Bit
7:5
2:0
4
3
Reserved
ACPI Enable (ACPI_EN) — R/W.
0 = Disable
1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the ACPI power
Reserved
SCI IRQ Select (SCI_IRQ_SEL) — R/W.
Specifies on which IRQ the SCI will internally appear. If not using the APIC, the SCI must be routed
to IRQ9–11, and that interrupt is not sharable with the SERIRQ stream, but is shareable with other
PCI interrupts. If using the APIC, the SCI can also be mapped to IRQ20–23, and can be shared with
other interrupts.
Bits
000
001
010
011
100
101
110
111
NOTE: When the TCO interrupt is mapped to APIC interrupts 9, 10 or 11, the signal is in fact active
management function is enabled. Note that the APM power management ranges (B2/B3h) are
always enabled and are not affected by this bit.
high. When the TCO interrupt is mapped to IRQ 20, 21, 22, or 23, the signal is active low
and can be shared with PCI interrupts that may be mapped to those same signals (IRQs).
SCI Map
IRQ9
IRQ10
IRQ11
Reserved
IRQ20 (Only available if APIC enabled)
IRQ21 (Only available if APIC enabled)
IRQ22 (Only available if APIC enabled)
IRQ23 (Only available if APIC enabled)
44h
00h
No
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Usage:
Power Well:
R/W
8 bit
ACPI, Legacy
Core
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