FW82801EB Intel, FW82801EB Datasheet - Page 200

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.19.2.3
5.19.2.4
200
Table 89. Command Register, Status Register and TD Status Bit Interaction
Command Register, Status Register,
and TD Status Bit Interaction
NOTES:
Note that if a NAK or STALL response is received from a SETUP transaction, a Time Out Error is
reported. This causes the Error counter to decrement and the CRC/Time-out Error status bit to be
set within the TD Control and Status DWord during write back. If the Error counter changes from 1
to 0, the Active bit will be reset to 0 and Stalled bit to 1 as normal.
Transfer Queuing
Transfer Queues are used to implement a guaranteed data delivery stream to a USB Endpoint.
Transfer Queues are composed of two parts: a Queue Header (QH) and a linked list. The linked list
of TDs and QHs has an indeterminate length (0 to n).
The QH contains two link pointers and is organized as two contiguous DWords. The first DWord is
a horizontal pointer (Queue Head Link Pointer), used to link a single transfer queue with either
another transfer queue, or a TD (target data structure depends on Q bit). If the T bit is set, this QH
1. Only If error counter counted down from 1 to 0
2. Suspend mode can be entered only when Run/Stop bit is 0
CRC/Time Out Error
Illegal PID, PID Error,
Max Length (illegal)
PCI Master/Target Abort
Suspend Mode
Resume Received and
Suspend Mode = 1
Run/Stop = 0
Config Flag Set
HC Reset/Global Reset
IOC = 1 in TD Status
Stall
Bit Stuff/Data Buffer Error
Short Packet Detect
Condition
Set USB Error Int bit
Clear Run/Stop bit in command register
Set HC Process Error and HC Halted bits
Clear Run/Stop bit in command register
Set Host System Error and HC Halted bits
Clear Run/Stop bit in command register
Set HC Halted bit
Set Resume received bit
Clear Run/Stop bit in command register
Set HC Halted bit
Set Config Flag in command register
Clear Run/Stop and Config Flag in command
register
Clear USB Int, USB Error Int, Resume received,
Host System Error, HC Process Error, and HC
Halted bits
Set USB Int bit
Set USB Error Int bit
Set USB Error Int bit
Set USB Int bit
Intel
®
ICH5 USB Status Register Actions
1
1
, Clear HC Halted bit
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
2
Clear Active bit
Stall bit
Clear Active bit
Stall bit
Clear Active bit
Stall bit
Clear Active bit
TD Status Register
1
1
Actions
1
1
1
and set
and set
and set