FW82801EB Intel, FW82801EB Datasheet - Page 129

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.8.5
5.8.5.1
5.8.5.2
5.8.6
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Masking on an Individual Interrupt Request
Masking Interrupts
Each interrupt request can be masked individually by the Interrupt Mask Register (IMR). This
register is programmed through OCW1. Each bit in the IMR masks one interrupt channel. Masking
IRQ2 on the master controller masks all requests for service from the slave controller.
Special Mask Mode
Some applications may require an interrupt service routine to dynamically alter the system priority
structure during its execution under software control. For example, the routine may wish to inhibit
lower priority requests for a portion of its execution but enable some of them for another portion.
The special mask mode enables all interrupts not masked by a bit set in the Mask register.
Normally, when an interrupt service routine acknowledges an interrupt without issuing an EOI to
clear the ISR bit, the interrupt controller inhibits all lower priority requests. In the special mask
mode, any interrupts may be selectively enabled by loading the Mask Register with the appropriate
pattern. The special mask mode is set by OCW3 where: SSMM=1, SMM=1, and cleared where
SSMM=1, SMM=0.
Steering PCI Interrupts
The ICH5 can be programmed to allow PIRQA#-PIRQH# to be internally routed to interrupts 3–7,
9–12, 14 or 15. The assignment is programmable through the PIRQx Route Control registers,
located at 60–63h and 68–6Bh in function 0. One or more PIRQx# lines can be routed to the same
IRQx input. If interrupt steering is not required, the Route registers can be programmed to disable
steering.
The PIRQx# lines are defined as active low, level sensitive to allow multiple interrupts on a PCI
Board to share a single line across the connector. When a PIRQx# is routed to specified IRQ line,
software must change the IRQ's corresponding ELCR bit to level sensitive mode. The ICH5
internally inverts the PIRQx# line to send an active high level to the PIC. When a PCI interrupt is
routed onto the PIC, the selected IRQ can no longer be used by an ISA device (through SERIRQ).
However, active low non-ISA interrupts can share their interrupt with PCI interrupts.
Internal sources of the PIRQs, including SCI and TCO interrupts, cause the external PIRQ to be
asserted. The ICH5 receives the PIRQ input, like all of the other external sources, and routes it
accordingly.
Functional Description
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