FW82801EB Intel, FW82801EB Datasheet - Page 93

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.2.2.3
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
PCI Power Management
Enhanced support for the power management standard, PCI Local Bus Specification, Revision 2.3,
is provided in the ICH5 integrated LAN controller. The LAN controller supports a large set of
wake-up packets and the capability to wake the system from a low power state on a link status
change. The LAN controller enables the host system to be in a sleep state and remain virtually
connected to the network.
After a power management event or link status change is detected, the LAN controller wakes the
host system. The sections below describe these events, the LAN controller power states, and
estimated power consumption at each power state.
Power States
The LAN controller contains power management registers for PCI, and implements four power
states, D0 through D3, which vary from maximum power consumption at D0 to the minimum
power consumption at D3. PCI transactions are only allowed in the D0 state, except for host
accesses to the LAN controller’s PCI configuration registers. The D1 and D2 power management
states enable intermediate power savings while providing the system wake-up capabilities. In the
D3 cold state, the LAN controller can provide wake-up capabilities. Wake-up indications from the
LAN controller are provided by the Power Management Event (PME#) signal.
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D0 Power State
The device is fully functional in the D0 power state. In this state, the LAN controller receives
full power and should be providing full functionality. In the LAN controller the D0 state is
partitioned into two substates, D0 Uninitialized (D0u) and D0 Active (D0a).
D0u is the LAN controller’s initial power state following a PCI RST#. While in the D0u state,
the LAN controller has PCI slave functionality to support its initialization by the host and
supports Wake on LAN mode. Initialization of the CSR, Memory, or I/O Base Address
Registers in the PCI Configuration space switches the LAN controller from the D0u state to
the D0a state.
In the D0a state, the LAN controller provides its full functionality and consumes its nominal
power. In addition, the LAN controller supports wake on link status change
(see
signal (in other words, a clock frequency greater than 16 MHz) for proper operation. The LAN
controller supports a dynamic standby mode. In this mode, the LAN controller is able to save
almost as much power as it does in the static power-down states. The transition to or from
standby is done dynamically by the LAN controller and is transparent to the software.
D1 Power State
In order for a device to meet the D1 power state requirements, as specified in the Advanced
Configuration and Power Interface, Version 2.0b Specification, it must not allow bus
transmission or interrupts; however, bus reception is allowed. Therefore, device context may
be lost and the LAN controller does not initiate any PCI activity. In this state, the LAN
controller responds only to PCI accesses to its configuration space and system wake-up events.
The LAN controller retains link integrity and monitors the link for any wake-up events (e.g.,
wake-up packets or link status change). Following a wake-up event, the LAN controller asserts
the PME# signal.
Section
5.2.2.5). While it is active, the LAN controller requires a nominal PCI clock
Functional Description
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