FW82801EB Intel, FW82801EB Datasheet - Page 455

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

11.1.41
11.1.42
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
BFTD1—BIST FIS Transmit Data1 Register
(SATA–D31:F2)
Address Offset:
Default Value:
BFTD2—BIST FIS Transmit Data2 Register
(SATA–D31:F2)
Address Offset:
Default Value:
31:0
31:0
Bits
Bits
BIST FIS Transmit Data 1 — R/W. The data programmed into this register will form the contents of
the second DWord of any BIST FIS initiated by the Intel
contents will be used for BIST FIS initiated on port 0 or port 1. Although the 2nd and 3rd DWs of the
BIST FIS are only meaningful when the “T” bit of the BIST FIS is set to indicate “Far-End Transmit
mode”, this register’s contents will be transmitted as the BIST FIS 2nd DW regardless of whether or
not the “T” bit is indicated in the BFCS register.
BIST FIS Transmit Data 2 — R/W. The data programmed into this register will form the contents of
the third DWord of any BIST FIS initiated by the Intel
contents will be used for BIST FIS initiated on port 0 or port 1. Although the 2nd and 3rd DWs of the
BIST FIS are only meaningful when the “T” bit of the BIST FIS is set to indicate “Far-End Transmit
mode”, this register’s contents will be transmitted as the BIST FIS 3rd DW regardless of whether or
not the “T” bit is indicated in the BFCS register.
E4h
00000000h
E8h
00000000h
–
–
E7h
EBh
Description
Description
Attribute:
Size:
Attribute:
Size:
®
SATA Controller Registers (D31:F2)
ICH5. This register is not port specific — its
®
ICH5. This register is not port specific — its
R/W
32 bits
R/W
32 bits
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