FW82801EB Intel, FW82801EB Datasheet - Page 543

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

15.1.20
15.1.21
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
CFG—Configuration Register
(Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
This register is used to specify the ID for the secondary and tertiary codecs for I/O accesses. This
register is not affected by the D3
PID—PCI Power Management Capability Identification
Register (Audio—D31:F5)
Address Offset:
Default Value:
Lockable:
15:8
Bit
7:1
Bit
7:0
0
Reserved—RO.
I/O Space Enable (IOSE) — R/W.
0 = Disable. The IOS bit at offset 04h and the I/O space BARs at offset 10h and 14h become read
1 = Enable
Next Capability (NEXT) — RO. This field indicates that the next item in the list is at offset 00h.
Capability ID (CAP) — RO.This field indicates that this pointer is a message signaled interrupt
capability.
only registers. Additionally, bit 0 of the I/O BARs at offsets 10h and 14h are hardwired to 0
when this bit is 0. This is the default state for the I/O BARs. BIOS must explicitly set this bit to
allow a legacy driver to work.
41h
00h
No
50
0001h
No
–
51h
HOT
to D0 transition.
AC ’97 Audio Controller Registers (D31:F5)
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/W
8 bits
Core
RO
16 bits
Core
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