FW82801EB Intel, FW82801EB Datasheet - Page 297

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

7.2.11
7.2.12
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
GENCNTL—General Control Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
GENSTA—General Status Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
Bit
7:4
Bit
7:3
3
2
1
0
2
1
0
Reserved. These bits should be set to 0000b.
LAN Connect Software Reset
0 = Cleared by software to begin normal LAN Connect operating mode. Software must not attempt
1 = Software can set this bit to force a reset condition on the LAN Connect interface.
Reserved. This bit should be set to 0.
Deep Power-Down on Link Down Enable
0 = Disable
1 = Enable. The Intel
Reserved
Reserved
Duplex Mode — RO. This bit indicates the wire duplex mode.
0 = Half duplex
1 = Full duplex
Speed — RO. This bit indicates the wire speed.
0 = 10 Mbps
1 = 100 Mbps
Link Status Indication — RO. This bit indicates the status of the link.
0 = Invalid
1 = Valid
to access the LAN Connect interface for at least 1 ms after clearing this bit.
3 mA) in the D2 and D3 power states while the link is down. In this state, the LAN controller
does not keep link integrity. This state is not supported for point-to-point connection of two end
stations.
1Ch
00h
1Dh
00h
®
ICH5’s internal LAN controller may enter a deep power-down state (sub-
—
R/W.
Description
Description
—
Attribute:
Size:
Attribute:
Size:
R/W.
LAN Controller Registers (B1:D8:F0)
R/W
8 bits
RO
8 bits
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