FW82801EB Intel, FW82801EB Datasheet - Page 3

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
®
ICH5/ICH5R Features
The Intel
published specifications. Current characterized errata are available on request.
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PCI Bus Interface
Integrated LAN Controller
New: Integrated Serial ATA Host Controllers
Integrated IDE Controller
USB 2.0
AC-Link for Audio and Telephony Codecs
Interrupt Controller
High-Precision Event Timers
New: 1.5 V operation with 3.3 V I/O
Timers Based on 82C54
— New: Supports PCI Revision 2.3 Specification at
— 6 available PCI REQ/GNT pairs
— One PCI REQ/GNT pair can be given higher
— Support for 44-bit addressing on PCI using DAC
— New: Integrated ASF Management Controller
— WfM 2.0 and IEEE 802.3 Compliant
— LAN Connect Interface (LCI)
— 10/100 Mbit/sec Ethernet Support
— Independent DMA operation on two ports.
— Data transfer rates up to 1.5 Gb/s (150 MB/s).
— RAID Level 0 Support (ICH5R Only)
— Supports “Native Mode” Register and Interrupts
— Independent timing of up to 4 drives
— Ultra ATA/100/66/33, BMIDE and PIO modes
— Tri-state modes to enable swap bay
— New: Includes 4 UHCI Host Controllers,
— Includes 1 EHCI Host Controller that supports all
— Includes 1 USB 2.0 high-speed debug port
— Supports wake-up from sleeping states S1–S5
— Supports legacy Keyboard/Mouse software
— Support for 3 AC ‘97 2.3 codecs.
— Independent bus master logic for 8 channels (PCM
— Support for up to six channels of PCM audio
— Supports wake-up events
— Supports up to 8 PCI interrupt pins
— Supports PCI 2.3 Message Signaled Interrupts
— Two cascaded 82C59 with 15 interrupts
— Integrated I/O APIC capability with 24 interrupts
— Supports Front Side Bus interrupt delivery
— Advanced operating system interrupt scheduling
— 5V tolerant buffers on IDE, PCI, USB Over-
— System timer, Refresh request, Speaker tone
®
33 MHz
arbitration priority (intended for external 1394
host controller)
protocol
increasing the number of external ports to eight
eight ports
In/Out, PCM2 In, Mic 1 Input, Mic 2 Input,
Modem In/Out, S/PDIF Out)
output (full AC3 decode)
current and Legacy signals
output
ICH5 / ICH5R may contain design defects or errors known as errata which may cause the products to deviate from
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New: Integrated 1.5 V Voltage Regulator (INTVR) for
the Suspend wells
Power Management Logic
External Glue Integration
Flash BIOS I/F supports BIOS Memory size up to
8 Mbytes
Low Pin Count (LPC) I/F
Enhanced DMA Controller
Real-Time Clock
System TCO Reduction Circuits
SMBus
GPIO
Package 31x31 mm 460 mBGA
— New: ACPI 2.0 compliant
— ACPI-defined power states (C1, S3–S5)
— ACPI Power Management Timer
— PCI PME# support
— SMI# generation
— All registers readable/restorable for proper resume
— Support for APM-based legacy power
— Integrated Pull-up, Pull-down and Series
— Integrated Pull-down and Series resistors on USB
— Supports two Master/DMA devices.
— Support for Security Devices connected to LPC.
— Two cascaded 8237 DMA controllers
— PCI DMA: Supports PC/PCI — Includes two
— Supports LPC DMA
— Supports DMA Collection Buffer to provide Type-
— 256-byte battery-backed CMOS RAM
— Integrated oscillator components
— Lower Power DC/DC Converter implementation
— Timers to generate SMI# and Reset upon detection
— Timers to detect improper processor reset
— Integrated processor frequency strap logic
— Supports ability to disable external devices
— New: Provides independent manageability bus
— Supports SMBus 2.0 Specification
— Host interface allows processor to communicate
— Slave interface allows an internal or external
— Compatible with most 2-Wire components that are
— TTL, Open-Drain, Inversion
from 0 V suspend states
management for non-ACPI implementations
Termination resistors on IDE, processor I/F
PC/PCI REQ#/GNT# pairs
F DMA performance for all DMA channels
of system hang
through SMLink interface.
via SMBus
Microcontroller to access system resources
also I
2
C compatible
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