FW82801EB Intel, FW82801EB Datasheet - Page 508

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

EHCI Controller Registers (D29:F7)
13.2.13
508
PORTSC—Port N Status and Control Register
Offset:
Attribute:
Default Value:
A host controller must implement one or more port registers. Software uses the N_Port information
from the Structural Parameters Register to determine how many ports need to be serviced. All ports
have the structure defined below. Software must not write to unreported Port Status and Control
Registers.
This register is in the suspend power well. It is only reset by hardware when the suspend power is
initially applied or in response to a host controller reset. The initial conditions of a port are:
When a device is attached, the port state transitions to the attached state and system software will
process this as with any status change notification. Refer to Section 4 of the Enhanced Host
Controller Interface Specification for Universal Serial Bus, Revision 1.0 for operational
requirements for how change events interact with port suspend mode.
•
•
31:23
Bit
22
21
20
No device connected
Port disabled.
Reserved. These bits are reserved for future use and will return a value of 0s when read.
Wake on Overcurrent Enable (WKOC_E) — R/W.
0 = Disable (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Wake on Disconnect Enable (WKDSCNNT_E) — R/W.
0 = Disable (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Wake on Connect Enable (WKCNNT_E) — R/W.
0 = Disable (Default)
1 = Enable. Writing this bit to a 1 enables the setting of the PME Status bit in the Power
Management Control/Status Register (offset 54, bit 15) when the overcurrent Active bit (bit 4 of
this register) is set.
Management Control/Status Register (offset 54, bit 15) when the Current Connect Status
changes from connected to disconnected (i.e., bit 0 of this register changes from 1 to 0).
Management Control/Status Register (offset 54, bit 15) when the Current Connect Status
changes from disconnected to connected (i.e., bit 0 of this register changes from 0 to 1).
Port 0: CAPLENGTH + 44
Port 1: CAPLENGTH + 48
Port 2: CAPLENGTH + 4C
Port 3: CAPLENGTH + 50
Port 4: CAPLENGTH + 54
Port 5: CAPLENGTH + 58
Port 6: CAPLENGTH + 5C
Port 7: CAPLENGTH + 60
R/W, R/WC, RO
00003000h
–
–
–
–
–
–
–
–
47h
4Bh
53h
57h
5Bh
63h
4Fh
5Fh
Description
Intel
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
32 bits