FW82801EB Intel, FW82801EB Datasheet - Page 639

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Register Index
Intel
®
Table 204. Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
Vendor Identification
Device Identification
PCI Command
PCI Device Status
Revision Identification
Programming Interface
Sub Class Code
Base Class Code
Cache Line Size
Master Latency Timer
Header Type
CSR Memory-Mapped
Base Address
CSR I/O-Mapped Base
Address
Subsystem Vendor ID
Subsystem ID
Capabilities Pointer
Interrupt Line Register
Interrupt Pin Register
Minimum Grant Register
Maximum Latency Register
®
Register Name
ICH5 PCI Configuration Registers (Sheet 1 of 11)
2C – 2Dh
2E – 2Fh
00 – 01h
02 – 03h
04 – 05h
06 – 07h
10 – 13h
14 – 17h
Offset
0Ah
0Bh
0Ch
0Dh
0Eh
3Ch
3Dh
3Eh
3Fh
08h
09h
34h
LAN Controller (B1:D8:F0)
Section 7.1.1, “VID—Vendor Identification Register (LAN
Controller—B1:D8:F0)” on page 276
Section 7.1.2, “DID—Device Identification Register (LAN
Controller—B1:D8:F0)” on page 276
Section 7.1.3, “PCICMD—PCI Command Register (LAN
Controller—B1:D8:F0)” on page 277
Section 7.1.4, “PCISTS—PCI Status Register (LAN Controller—
B1:D8:F0)” on page 278
Section 7.1.5, “RID—Revision Identification Register (LAN
Controller—B1:D8:F0)” on page 279
Section 7.1.6, “SCC—Sub-Class Code Register (LAN
Controller—B1:D8:F0)” on page 279
Section 7.1.7, “BCC—Base-Class Code Register (LAN
Controller—B1:D8:F0)” on page 279
Section 7.1.8, “CLS—Cache Line Size Register (LAN
Controller—B1:D8:F0)” on page 280
Section 7.1.9, “PMLT—Primary Master Latency Timer Register
(LAN Controller—B1:D8:F0)” on page 280
Section 7.1.10, “HEADTYP—Header Type Register (LAN
Controller—B1:D8:F0)” on page 280
Section 7.1.11, “CSR_MEM_BASE — CSR Memory-Mapped
Base Address Register (LAN Controller—B1:D8:F0)” on
page 281
Section 7.1.12, “CSR_IO_BASE — CSR I/O-Mapped Base
Address Register (LAN Controller—B1:D8:F0)” on page 281
Section 7.1.13, “SVID — Subsystem Vendor Identification
Register (LAN Controller—B1:D8:F0)” on page 281
Section 7.1.14, “SID — Subsystem Identification Register (LAN
Controller—B1:D8:F0)” on page 282
Section 7.1.15, “CAP_PTR — Capabilities Pointer Register
(LAN Controller—B1:D8:F0)” on page 282
Section 7.1.16, “INT_LN — Interrupt Line Register (LAN
Controller—B1:D8:F0)” on page 282
Section 7.1.17, “INT_PN — Interrupt Pin Register (LAN
Controller—B1:D8:F0)” on page 283
Section 7.1.18, “MIN_GNT — Minimum Grant Register (LAN
Controller—B1:D8:F0)” on page 283
Section 7.1.19, “MAX_LAT — Maximum Latency Register (LAN
Controller—B1:D8:F0)” on page 283
Datasheet Section and Location
Register Index
A
639