FW82801EB Intel, FW82801EB Datasheet - Page 528

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

SMBus Controller Registers (D31:F3)
14.2.12
.
14.2.13
528
Note: This register is in the resume well and is reset by RSMRST#.
AUX_CTL—Auxiliary Control Register
(SMBUS—D31:F3)
Register Offset:
Default Value:
Lockable:
SMLINK_PIN_CTL—SMLink Pin Control Register
(SMBUS—D31:F3)
Register Offset:
Default Value:
This register is only applicable in the TCO compatible mode.
Bit
7:2
Bit
7:3
1
0
2
1
0
Reserved
Enable 32-Byte Buffer (E32B) — R/W.
0 = Disable
1 = Enable. When set, the Host Block Data register is a pointer into a 32-byte buffer, as opposed to
Automatically Append CRC (AAC) — R/W.
0 = ICH5 will not automatically append the CRC.
1 = The ICH5 will automatically append the CRC. This bit must not be changed during SMBus
Reserved
SMLINK_CLK_CTL — R/W.
0 = Intel
1 = The SMLINK0 pin is not overdriven low. The other SMLINK logic controls the state of the pin.
SMLINK1_CUR_STS — RO. This read-only bit has a default value that is dependent on an external
signal level. This pin returns the value on the SMLINK1 pin. This allows software to read the current
state of the pin.
0 = Low
1 = High
SMLINK0_CUR_STS — RO. This read-only bit has a default value that is dependent on an external
signal level. This pin returns the value on the SMLINK0 pin. This allows software to read the current
state of the pin.
0 = Low
1 = High
a single register. This enables the block commands to transfer or receive up to 32-bytes before
the Intel
transactions or undetermined behavior will result. It should be programmed only once during the
lifetime of the function.
otherwise indicate for the SMLINK0 pin.
(Default)
®
ICH5 will drive the SMLINK0 pin low, independent of what the other SMLINK logic would
0Dh
00h
No
0Eh
See below
®
ICH5 generates an interrupt.
Intel
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
RW
8 bits
Resume
R/W, RO
8 bits