FW82801EB Intel, FW82801EB Datasheet - Page 510

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

EHCI Controller Registers (D29:F7)
510
Bit
7
6
5
4
3
Suspend — R/W.
0 = Port not in suspend state.(Default)
1 = Port in suspend state.
Port Enabled Bit and Suspend bit of this register define the port states as follows:
Port Enabled, Suspend Bits
When in suspend state, downstream propagation of data is blocked on this port, except for port
reset. Note that the bit status does not change until the port is suspended and that there may be a
delay in suspending a port depending on the activity on the port.
The host controller will unconditionally set this bit to a 0 when software sets the Force Port Resume
bit to a 0 (from a 1). A write of 0 to this bit is ignored by the host controller.
If host software sets this bit to a 1 when the port is not enabled (i.e., Port enabled bit is a 0) the
results are undefined.
Force Port Resume — R/W.
0 = No resume (K-state) detected/driven on port. (Default)
1 = Resume detected/driven on port. Software sets this bit to a 1 to drive resume signaling. The
NOTE: When the EHCI controller owns the port, the resume sequence follows the defined
Overcurrent Change — R/WC. The functionality of this bit is not dependent upon the port owner.
Software clears this bit by writing a 1 to it.
0 = No change. (Default)
1 = There is a change to Overcurrent Active.
Overcurrent Active — RO.
0 = This port does not have an overcurrent condition. (Default)
1 = This port currently has an overcurrent condition. This bit will automatically transition from 1 to 0
Port Enable/Disable Change — R/WC. For the root hub, this bit gets set to a 1 only when a port is
disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the
Universal Serial Bus Revision 2.0 Specification for the definition of a port error). This bit is not set
due to the Disabled-to-Enabled transition, nor due to a disconnect. Software clears this bit by writing
a 1 to it.
0 = No change in status. (Default).
1 = Port enabled/disabled status has changed.
Host Controller sets this bit to a 1 if a J-to-K transition is detected while the port is in the
Suspend state. When this bit transitions to a 1 because a J-to-K transition is detected, the Port
Change Detect bit in the USB2.0_STS register is also set to a 1. If software sets this bit to a 1,
the host controller must not set the Port Change Detect bit.
when the over current condition is removed. The Intel
when the overcurrent active bit is 1.
sequence documented in the Universal Serial Bus Revision 2.0 Specification. The resume
signaling (Full-speed 'K') is driven on the port as long as this bit remains a 1. Software must
appropriately time the Resume and set this bit to a 0 when the appropriate amount of time
has elapsed. Writing a 0 (from 1) causes the port to return to high-speed mode (forcing the
bus below the port into a high-speed idle). This bit will remain a 1 until the port has switched
to the high-speed idle.
0, X
1, 0
1, 1
Port State
Disable
Enable
Suspend
Description
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
®
ICH5 automatically disables the port