FW82801EB Intel, FW82801EB Datasheet - Page 376

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.8
376
Table 149. Power Management PCI Register Address Map (PM—D31:F0)
Power Management
(PM—D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0 space, as
well as a separate I/O range. Each register is described below. Unless otherwise indicate, bits are in
the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to a reserved
bit, the value should always be 0. Software should not attempt to use the value read from a reserved
bit, as it may not be consistently 1 or 0.
Table 149
only those registers dedicated for power management. Some of the registers are only used for
Legacy Power management schemes.
40h–43h
C4–CAh
B8–BBh
Offset
ADh
CCh
AEh
44h
A0h
A2h
A4h
A8h
C0
shows a small part of the configuration space for PCI Device 31: Function 0. It includes
MON[n]_TRP_RNG
GEN_PMCON_1
GEN_PMCON_2
GEN_PMCON_3
MON_TRP_MSK
SATA_RD_CFG
TRP_FWD_EN
STPCLK_DEL
ACPI_BASE
ACPI_CNTL
GPI_ROUT
Mnemonic
USB_TDD
ACPI Base Address
ACPI Control
General Power Management
Configuration 1
General Power Management
Configuration 2
General Power Management
Configuration 3
Stop Clock Delay Register
USB Transient Disconnect Detect
SATA RAID Configuration (Intel
ICH5R Only)
GPI Route Control
I/O Monitor Trap Forwarding Enable
I/O Monitor[4:7] Trap Range
I/O Monitor Trap Range Mask
PCI Configuration Registers
Register Name
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
®
82801ER
00000001h
00000000h
Default
0000h
0000h
0000h
0000h
0Dh
C0h
00h
00h
00h
00h
R/W, R/WC
R/W, R/WC
R/W, RO,
(special)
R/WO
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W