FW82801EB Intel, FW82801EB Datasheet - Page 52

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Signal Description
2.4
2.5
52
Table 6.
Table 7.
Flash BIOS Interface
Flash BIOS Interface Signals
PCI Interface
PCI Interface Signals (Sheet 1 of 3)
C/BE[3:0]#
LFRAME#
DEVSEL#
AD[31:0]
FRAME#
FB[3:0] /
LAD[3:0]
Name
Name
FB4 /
Type
Type
I/O
I/O
I/O
I/O
I/O
I/O
PCI Address/Data: AD[31:0] are the signals of the multiplexed address and data
bus. During the first clock of a transaction, AD[31:0] contain a physical address
(32 bits). During subsequent clocks, AD[31:0] contain data. The Intel
drive all 0s on AD[31:0] during the address phase of all PCI Special Cycles.
Bus Command and Byte Enables: The command and byte enable signals are
multiplexed on the same PCI pins. During the address phase of a transaction,
C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# define the
Byte Enables.
All command encodings not shown are reserved. The ICH5 does not decode
reserved values, and therefore will not respond if a PCI master generates a cycle
using 1 of the reserved values.
Device Select: The ICH5 asserts DEVSEL# to claim a PCI transaction. As an
output, the ICH5 asserts DEVSEL# when a PCI master peripheral attempts an
access to an internal ICH5 address or an address destined for the hub interface
(main memory or AGP). As an input, DEVSEL# indicates the response to an ICH5-
initiated transaction on the PCI bus. DEVSEL# is tri-stated from the leading edge of
PCIRST#. DEVSEL# remains tri-stated by the ICH5 until driven by a Target device.
Cycle Frame: The current Initiator drives FRAME# to indicate the beginning and
duration of a PCI transaction. While the initiator asserts FRAME#, data transfers
continue. When the initiator negates FRAME#, the transaction is in the final data
phase. FRAME# is an input to the ICH5 when the ICH5 is the target, and FRAME#
is an output from the ICH5 when the ICH5 is the Initiator. FRAME# remains tri-
stated by the ICH5 until driven by an Initiator.
Flash BIOS Signals: These signals are multiplexed with the LPC address
signals.
Flash BIOS Signals: This signal is multiplexed with the LPC LFRAME# signal.
C/BE[3:0]#
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 1 0
0 1 1 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 1 0
1 1 1 1
Command Type
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Memory Read Line
Memory Write and Invalidate
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Description
Description
®
ICH5 will