FW82801EB Intel, FW82801EB Datasheet - Page 178

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.16.2.2
5.16.2.3
5.16.2.4
178
Warning:
Figure 18. Physical Region Descriptor Table Entry
Line Buffer
A single line buffer exists for the ICH5 Bus master IDE interface. This buffer is not shared with
any other function. The buffer is maintained in either the read state or the write state. Memory
writes are typically 4-DWord bursts and invalid DWords have C/BE[3:0]#=0Fh. The line buffer
allows burst data transfers to proceed at peak transfer rates.
The Bus Master IDE Active bit in Bus Master IDE Status register is reset automatically when the
controller has transferred all data associated with a Descriptor Table (as determined by EOT bit in
last PRD). The IDE Interrupt Status bit is set when the IDE device generates an interrupt. These
events may occur prior to line buffer emptying for memory writes. If either of these conditions
exist, all PCI Master non-Memory read accesses to ICH5 are retried until all data in the line buffers
has been transferred to memory.
Bus Master IDE Timings
The timing modes used for Bus Master IDE transfers are identical to those for PIO transfers. The
DMA Timing Enable Only bits in IDE Timing register can be used to program fast timing mode for
DMA transactions only. This is useful for IDE devices whose DMA transfer timings are faster that
its PIO transfer timings. The IDE device DMA request signal is sampled on the same PCI clock
that DIOR# or DIOW# is deasserted. If inactive, the DMA Acknowledge signal is deasserted on
the next PCI clock and no more transfers take place until DMA request is asserted again.
Interrupts
Legacy Mode
The ICH5 is connected to IRQ14 for the primary interrupt and IRQ15 for the secondary interrupt.
This connection is done from the ISA pin, before any mask registers. This implies the following:
In this mode, the ICH5 does not drive the PCI Interrupt associated with this function. That is only
used in native mode.
•
Bus Master IDE devices are connected directly off of ICH5. IDE interrupts cannot be
communicated through PCI devices or the serial stream.
EOT
Byte 3
Memory Region Physical Base Address [31:1]
Reserved
Byte 2
Byte 1
Byte Count [15:1]
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Byte 0
o
o
Main Memory
Memory
Region