FW82801EB Intel, FW82801EB Datasheet - Page 177

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.16.1.6
5.16.2
5.16.2.1
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Bus Master Function
Physical Region Descriptor Format
PIO IDE Data Port Prefetching and Posting
The ICH5 can be programmed via the IDETIM registers to allow data to be posted to and
prefetched from the IDE data ports.
Data prefetching is initiated when a data port read occurs. The read prefetch eliminates latency to
the IDE data ports and allows them to be performed back to back for the highest possible PIO data
transfer rates. The first data port read of a sector is called the demand read. Subsequent data port
reads from the sector are called prefetch reads. The demand read and all prefetch reads much be of
the same size (16 or 32 bits).
Data posting is performed for writes to the IDE data ports. The transaction is completed on the PCI
bus after the data is received by the ICH5. The ICH5 then runs the IDE cycle to transfer the data to
the drive. If the ICH5 write buffer is non-empty and an unrelated (non-data or opposite channel)
IDE transaction occurs, that transaction will be stalled until all current data in the write buffer is
transferred to the drive.
The ICH5 can act as a PCI Bus master on behalf of an IDE slave device. Two PCI Bus master
channels are provided, one channel for each IDE connector (primary and secondary). By
performing the IDE data transfer as a PCI Bus master, the ICH5 off-loads the processor and
improves system performance in multitasking environments. Both devices attached to a connector
can be programmed for bus master transfers, but only one device per connector can be active at a
time.
The physical memory region to be transferred is described by a Physical Region Descriptor (PRD).
The PRDs are stored sequentially in a Descriptor Table in memory. The data transfer proceeds until
all regions described by the PRDs in the table have been transferred. Note that the ICH5 bus master
IDE function does not support memory regions or Descriptor tables located on ISA.
Descriptor Tables must not cross a 64-KB boundary. Each PRD entry in the table is 8 bytes in
length. The first 4 bytes specify the byte address of a physical memory region. This memory region
must be DWord-aligned and must not cross a 64-Kbyte boundary. The next two bytes specify the
size or transfer count of the region in bytes (64-Kbyte limit per region). A value of 0 in these two
bytes indicates 64 Kbytes (thus the minimum transfer count is 1). If bit 7 (EOT) of the last byte is a
1, it indicates that this is the final PRD in the Descriptor table. Bus master operation terminates
when the last descriptor has been retired.
When the Bus Master IDE controller is reading data from the memory regions, bit 1 of the Base
Address is masked and byte enables are asserted for all read transfers. When writing data, bit 1 of
the Base Address is not masked and if set, will cause the lower Word byte enables to be deasserted
for the first DWord transfer. The write to PCI typically consists of a 32-byte cache line. If valid data
ends prior to end of the cache line, the byte enables will be deasserted for invalid data.
The total sum of the byte counts in every PRD of the descriptor table must be equal to or greater
than the size of the disk transfer request. If greater than the disk transfer request, the driver must
terminate the bus master transaction (by setting bit 0 in the Bus Master IDE Command Register to
0) when the drive issues an interrupt to signal transfer completion.
Functional Description
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