FW82801EB Intel, FW82801EB Datasheet - Page 190

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
190
Warning:
During run-time, the value in the timer’s comparator value register will not be changed by the
hardware. Software can change the value.
Software must be careful when programming the comparator registers. If the value written to the
register is not sufficiently far in the future, then the counter may pass the value before it reaches the
register and the interrupt will be missed.
All three timers support non-periodic mode.
Periodic Mode
Timer 0 is the only timer that supports periodic mode. When Timer 0 is set up for periodic mode,
the software writes a value into the timer’s comparator value register. When the main counter value
matches the value in the timer’s comparator value register, an interrupt can be generated. The
hardware then automatically increases the value in the comparator value register by the last value
written to that register.
To make the periodic mode work properly, the main counter is typically written with a value of 0 so
that the first interrupt occurs at the right point for the comparator. If the main counter is not set to 0,
interrupts may not occur as expected.
During run-time, the value in the timer’s comparator value register can be read by software to find
out when the next periodic interrupt will be generated (not the rate at which it generates interrupts).
Software is expected to remember the last value written to the comparator’s value register (the rate
at which interrupts are generated).
If software wants to change the periodic rate, it should write a new value to the comparator value
register. At the point when the timer’s comparator indicates a match, this new value is added to
derive the next matching point.
If the software resets the main counter, the value in the comparator’s value register needs to reset as
well. This can be done by setting the TIMER0_VAL_SET_CNF bit. Again, to avoid race
conditions, this should be done with the main counter halted. The following usage model is
expected:
The Timer 0 Comparator Value register cannot be programmed reliably by a single 64-bit write in a
32-bit environment except if only the periodic rate is being changed during run-time. If the actual
Timer 0 Comparator Value needs to be reinitialized, then the following software solution will
always work regardless of the environment:
1. Software clears the ENABLE_CNF bit to prevent any interrupts
2. Software Clears the main counter by writing a value of 00h to it.
3. Software sets the TIMER0_VAL_SET_CNF bit.
4. Software writes the new value in the TIMER0_COMPARATOR_VAL register
5. Software sets the ENABLE_CNF bit to enable interrupts.
1. Set TIMER0_VAL_SET_CNF bit
2. Set the lower 32 bits of the Timer0 Comparator Value register
3. Set TIMER0_VAL_SET_CNF bit
4. 4) Set the upper 32 bits of the Timer0 Comparator Value register
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82801EB ICH5 / 82801ER ICH5R Datasheet