FW82801EB Intel, FW82801EB Datasheet - Page 493

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

13.1.28
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
SPECIAL_SMI—Intel Specific USB 2.0 SMI Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
Power Well:
31:30
29:22
12:6
Bit
Bit
13
21
20
5
4
3
2
1
0
SMI on OS Ownership Enable — R/W.
0 = Disable
1 = Enable. When this bit is a 1 AND the OS Ownership Change bit is 1, the host controller will
Reserved — RO. Hardwired to 00h
SMI on Async Advance Enable — R/W.
0 = Disable
1 = Enable. When this bit is a 1, and the SMI on Async Advance bit is a 1, the host controller will
SMI on Host System Error Enable — R/W.
0 = Disable
1 = Enable. When this bit is a 1, and the SMI on Host System Error is a 1, the host controller will
SMI on Frame List Rollover Enable — R/W.
0 = Disable
1 = Enable. When this bit is a 1, and the SMI on Frame List Rollover bit is a 1, the host controller
SMI on Port Change Enable — R/W.
0 = Disable
1 = Enable. When this bit is a 1, and the SMI on Port Change Detect bit is a 1, the host controller
SMI on USB Error Enable — R/W.
0 = Disable
1 = Enable. When this bit is a 1, and the SMI on USB Error bit is a 1, the host controller will issue an
SMI on USB Complete Enable — R/W.
0 = Disable
1 = Enable. When this bit is a 1, and the SMI on USB Complete bit is a 1, the host controller will
Reserved — RO. Hardwired to 00h
SMI on PortOwner — R/WC. Software clears these bits by writing a 1 to it.
0 = No Port Owner bit change.
1 = Bits 29:22 correspond to the Port Owner bits for ports 1 (22) through 8 (29). These bits are set
SMI on PMCSR — R/WC. Software clears these bits by writing a 1 to it.
0 = Power State bits not modified.
1 = Software modified the Power State bits in the Power Management Control/Status (PMCSR)
SMI on Async — R/WC. Software clears these bits by writing a 1 to it.
0 = No Async Schedule Enable bit change
1 = Async Schedule Enable bit transitioned from 1 to 0 or 0 to 1.
issue an SMI.
issue an SMI immediately.
issue an SMI.
will issue an SMI.
will issue an SMI.
SMI immediately.
issue an SMI immediately.
to 1 when the associated Port Owner bits transition from 0 to 1 or 1 to 0.
register.
Suspend
70
00000000h
–
73h
Description
Description
Attribute:
Size:
EHCI Controller Registers (D29:F7)
R/W, R/WC
32 bits
493