FW82801EB Intel, FW82801EB Datasheet - Page 333

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.1.24
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
BACK_CNTL—Backed Up Control Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
Bit
3:0
7
6
5
4
0 = Reserved. Hardwired to 0 forcing the reset state of the IDE pins to always be driven/tri-state
0 = Reserved. Hardwired to 0 forcing the reset state of the IDE pins to always be driven/tri-state
Top-Block Swap Mode (TOP_SWAP) — R/W. If Intel
low at rising edge of PWROK), then this bit CANNOT be cleared by software. The strap jumper
should be removed and the system rebooted.
This bit can not be overwritten after the Top-Swap Lock-Down bit is set.
0 = ICH5 will not invert A16. This bit is cleared by RTCRST# assertion, but not by any other type of
1 = ICH5 will invert A16 for cycles targeting flash BIOS space (does not affect access to flash BIOS
Enables CPU BIST (CPU_BIST_EN) — R/W.
0 = Disable
1 = The INIT# signal will be driven active when CPURST# is active. INIT# will go inactive with the
NOTE: This bit is in the Resume well and is reset by RSMRST#, but not by PCIRST# nor CF9h
CPU Frequency Strap (FREQ_STRAP[3:0]) — R/W. These bits determine the internal frequency
multiplier of the processor. These bits can be reset to 1111 based on an external pin strap or via the
RTCRST# input signal. Software must program this field based on the processor’s specified
frequency. Note that this field is only writable when the SAFE_MODE bit is cleared to 0, and
SAFE_MODE is only cleared by PWROK rising edge. These bits are in the RTC well.
(depending on the pin).
(depending on the pin).
reset.
feature space).
same timings as the other processor interface signals (Hold Time after CPURST# inactive).
Note that CPURST# is generated by the memory controller hub, but the ICH5 has a hub
interface special cycle that allows the ICH5 to control the assertion/deassertion of CPURST#.
writes.
D5h
0Fh (upon RTCRST# assertion low)
2Fh (if Top Swap Strap is active)
No
Description
LPC Interface Bridge Registers (D31:F0)
®
Attribute:
Size:
Power Well: RTC, Suspend (see bit
ICH5 is strapped for Top-Swap (GNTA# is
R/W, RO
8 bit
details)
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