FW82801EB Intel, FW82801EB Datasheet - Page 11

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
5.20
5.21
5.19.3 Data Encoding and Bit Stuffing ............................................................................204
5.19.4 Bus Protocol ........................................................................................................204
5.19.5 Packet Formats....................................................................................................207
5.19.6 USB Interrupts .....................................................................................................209
5.19.7 USB Power Management ....................................................................................212
5.19.8 USB Legacy Keyboard Operation........................................................................212
USB EHCI Host Controller (D29:F7).................................................................................215
5.20.1 EHC Initialization .................................................................................................215
5.20.2 Data Structures in Main Memory .........................................................................216
5.20.3 USB 2.0 Enhanced Host Controller DMA ............................................................216
5.20.4 Data Encoding and Bit Stuffing ............................................................................219
5.20.5 Packet Formats....................................................................................................219
5.20.6 USB 2.0 Interrupts and Error Conditions .............................................................220
5.20.7 USB 2.0 Power Management ..............................................................................221
5.20.8 Interaction with UHCI Host Controllers ................................................................222
5.20.9 USB 2.0 Legacy Keyboard Operation..................................................................225
5.20.10 USB 2.0 Based Debug Port .................................................................................226
SMBus Controller (D31:F3) ..............................................................................................231
5.21.1 Host Controller .....................................................................................................231
5.19.2.4 Transfer Queuing .................................................................................200
5.19.4.1 Bit Ordering..........................................................................................204
5.19.4.2 SYNC Field ..........................................................................................204
5.19.4.3 Packet Field Formats ...........................................................................205
5.19.4.4 Address Fields .....................................................................................206
5.19.4.5 Frame Number Field ............................................................................206
5.19.4.6 Data Field.............................................................................................206
5.19.4.7 Cyclic Redundancy Check (CRC)........................................................206
5.19.5.1 Token Packets .....................................................................................207
5.19.5.2 Start of Frame Packets ........................................................................207
5.19.5.3 Data Packets........................................................................................208
5.19.5.4 Handshake Packets .............................................................................208
5.19.5.5 Handshake Responses........................................................................209
5.19.6.1 Transaction Based Interrupts...............................................................209
5.19.6.2 Non-Transaction Based Interrupts .......................................................211
5.20.1.1 Power On .............................................................................................215
5.20.1.2 BIOS Initialization.................................................................................215
5.20.1.3 Driver Initialization................................................................................216
5.20.1.4 EHC Resets .........................................................................................216
5.20.3.1 Periodic List Execution.........................................................................216
5.20.3.2 Asynchronous List Execution...............................................................218
5.20.6.1 Aborts on USB 2.0-Initiated Memory Reads ........................................220
5.20.7.1 Pause Feature .....................................................................................221
5.20.7.2 Suspend Feature .................................................................................221
5.20.7.3 ACPI Device States .............................................................................221
5.20.7.4 ACPI System States ............................................................................222
5.20.8.1 Port-Routing Logic ...............................................................................223
5.20.8.2 Device Connects..................................................................................224
5.20.8.3 Device Disconnects .............................................................................225
5.20.8.4 Effect of Resets on Port-Routing Logic ................................................225
5.20.10.1 Theory of Operation ............................................................................226
5.21.1.1 Command Protocols ............................................................................232
5.21.1.2 I
2
C Behavior.........................................................................................242
Contents
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