FW82801EB Intel, FW82801EB Datasheet - Page 406

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.11.6
406
TCO2_STS—TCO2 Status Register
I/O Address:
Default Value:
Lockable:
15:5
Bit
Bit
2
1
0
4
3
2
1
0
TCO_INT_STS — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = SMI handler caused the interrupt by writing to the TCO_DAT_OUT register.
SW_TCO_SMI — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = Software caused an SMI# by writing to the TCO_DAT_IN register.
NMI2SMI_STS — RO.
0 = Cleared by clearing the associated NMI status bit.
1 = Set by the ICH5 when an SMI# occurs because an event occurred that would otherwise have
Reserved
SMLink Slave SMI Status (SMLINK_SLV_SMI_STS) — R/WC. Allow the software to go directly
into pre-determined sleep state. This avoids race conditions. Software clears this bit by writing a 1 to
it.
0 = The bit is reset by RSMRST#, but not due to the PCI Reset associated with exit from S3–S5
1 = Intel
Reserved
BOOT_STS — R/WC.
0 = Cleared by ICH5 based on RSMRST# or by software writing a 1 to this bit. Note that software
1 = Set to 1 when the SECOND_TO_STS bit goes from 0 to 1 and the processor has not fetched
If rebooting due to a second TCO timer timeout, and if the BOOT_STS bit is set, the ICH5 will reboot
using the ‘safe’ multiplier (1111). This allows the system to recover from a processor frequency
multiplier that is too high, and allows the BIOS to check the BOOT_STS bit at boot. If the bit is set
and the frequency multiplier is 1111, then the BIOS knows that the processor has been programmed
to an illegal multiplier.
SECOND_TO_STS — R/WC.
0 = Software clears this bit by writing a 1 to it, or by a RSMRST#.
1 = The ICH5 sets this bit to a 1 to indicate that the TCO timer timed out a second time (probably
Intruder Detect (INTRD_DET) — R/WC.
0 = Software clears this bit by writing a 1 to it, or by RTCRST# assertion.
1 = Set by ICH5 to indicate that an intrusion was detected. This bit is set even if the system is in G3
caused an NMI (because NMI2SMI_EN is set).
states.
should first clear the SECOND_TO_STS bit before writing a 1 to clear the BOOT_STS bit.
the first instruction.
due to system lock). If this bit is set and the NO_REBOOT configuration bit is 0, then the ICH5
will reboot the system after the second timeout. The reboot is done by asserting PCIRST#.
state.
®
ICH5 sets this bit to 1 when it receives the SMI message on the SMLink's Slave Interface.
TCOBASE +06h
0000h
No
Intel
Description
Description
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/WC
16-bit
Resume
(Except Bit 0, in RTC)