FW82801EB Intel, FW82801EB Datasheet - Page 377

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.8.1
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
GEN_PMCON_1—General PM Configuration 1 Register
(PM—D31:F0)
Offset Address:
Default Value:
Lockable:
15:11
8:7
3:2
1:0
Bit
10
9
6
5
4
Reserved
Reserved
PWRBTN_LVL — RO. This bit indicates the current state of the PWRBTN# signal.
0 = Low.
1 = High.
Reserved
i64_EN . Software sets this bit to indicate that the processor is an IA_64 processor, not an IA_32
processor. This may be used in various state machines where there are behavioral differences.
CPU SLP# Enable (CPUSLP_EN) — R/W.
0 = Disable
1 = Enables the CPUSLP# signal to go active in the S1 state. This reduces the processor
NOTE: CPUSLP# will go active on entry to S3, S4 and S5 even if this bit is not set.
SMI_LOCK — R/WO. When this bit is set, writes to the GLB_SMI_EN bit will have no effect.
Once the SMI_LOCK bit is set, writes of 0 to SMI_LOCK bit will have no effect (i.e., once set, this
bit can only be cleared by PCIRST#).
Reserved
Periodic SMI# Rate Select (PER_SMI_SEL) — R/W. Set by software to control the rate at
which periodic SMI# is generated.
00 = 1 minute
01 = 32 seconds
10 = 16 seconds
11 = 8 seconds
power.
A0h
00h
No
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Usage:
Power Well:
R/W, RO, R/WO
16-bit
ACPI, Legacy
Core
377