FW82801EB Intel, FW82801EB Datasheet - Page 364

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.5.3
9.5.4
364
Note: Writes to this register are only allowed by the processor and by masters on the ICH5’s PCI bus.
DAT—Data Register
(LPC I/F—D31:F0)
Memory Address
Default Value:
This is a 32-bit register specifying the data to be read or written to the register pointed to by the
Index register. This register can only be accessed in DWord quantities.
IRQPA—IRQ Pin Assertion Register
(LPC I/F—D31:F0)
Memory Address
Default Value:
The IRQ Pin Assertion Register is present to provide a mechanism to scale the number of interrupt
inputs into the I/O APIC without increasing the number of dedicated input pins. When a device that
supports this interrupt assertion protocol requires interrupt service, that device will issue a write to
this register. Bits 4:0 written to this register contain the IRQ number for this interrupt. The only
valid values are 0
always write a value of 0 for Bits 31:5.
See
Writes by devices on PCI buses above the ICH5 (e.g., a PCI segment on a P64H2) are not
supported.
31:5
Bit
7:0
Bit
4:0
Section 5.9.3
APIC Data — R/W. This is a 32-bit register for the data to be read or written to the APIC indirect
register pointed to by the Index register.
Reserved. To provide for future expansion, the processor should always write a value of 0 to Bits
31:5.
IRQ Number — WO. Bits 4:0 written to this register contain the IRQ number for this interrupt. The
only valid values are 0–23.
–
for more details on how PCI devices will use this field.
23. Bits 31:5 are ignored. To provide for future expansion, peripherals should
FEC0_0010h
00000000h
FEC0_0020h
N/A
Description
Intel
Description
Attribute:
Size:
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
32 bits
WO
32 bits