FW82801EB Intel, FW82801EB Datasheet - Page 105

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.4.1.3
5.4.1.4
Intel
®
Table 35. Cycle Type Bit Definitions
Table 36. Transfer Size Bit Definition
82801EB ICH5 / 82801ER ICH5R Datasheet
Cycle Type / Direction (CYCTYPE + DIR)
The ICH5 always drives bit 0 of this field to 0. Peripherals running bus master cycles must also
drive bit 0 to 0.
SIZE
Bits[3:2] are reserved. The ICH5 always drives them to 00. Peripherals running bus master cycles
are also supposed to drive 00 for bits 3:2; however, the ICH5 ignores those bits. Bits[1:0] are
encoded as listed in
Bits[3:2]
Bits[1:0]
00
00
01
01
10
10
11
00
01
10
11
Bit1
Table 35
8-bit transfer (1 byte)
16-bit transfer (2 bytes)
Reserved. The Intel
master cycle drives this combination, the ICH5 may abort the transfer.
32-bit transfer (4 bytes)
0
1
0
1
0
1
x
Table
I/O Read
I/O Write
Memory Read
Memory Write
DMA Read
DMA Write
Reserved. If a peripheral performing a bus master cycle generates this value, the
Intel
shows the valid bit encodings.
36.
®
ICH5 aborts the cycle.
®
ICH5 never drives this combination. If a peripheral running a bus
Size
Definition
Functional Description
105