FW82801EB Intel, FW82801EB Datasheet - Page 349

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

9.2.7
9.2.8
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
DMACH_MODE—DMA Channel Mode Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
DMA Clear Byte Pointer Register
(LPC I/F—D31:F0)
I/O Address:
Default Value:
Lockable:
Bit
7:6
3:2
1:0
Bit
7:0
5
4
DMA Transfer Mode — WO. Each DMA channel can be programmed in one of four different
modes:
00 = Demand mode
01 = Single mode
10 = Reserved
11 = Cascade mode
Address Increment/Decrement Select — WO. This bit controls address increment/decrement
during DMA transfers.
0 = Address increment. (default after part reset or Master Clear)
1 = Address decrement.
Autoinitialize Enable — WO.
0 = Autoinitialize feature is disabled and DMA transfers terminate on a terminal count. A part reset
1 = DMA restores the Base Address and Count registers to the current registers following a
DMA Transfer Type — WO. These bits represent the direction of the DMA transfer. When the
channel is programmed for cascade mode, (bits[7:6] = 11) the transfer type is irrelevant.
00 = Verify – No I/O or memory strobes generated
01 = Write – Data transferred from the I/O devices to memory
10 = Read – Data transferred from memory to the I/O device
11 = Illegal
DMA Channel Select — WO. These bits select the DMA Channel Mode Register that will be written
by bits [7:2].
00 = Channel 0 (4)
01 = Channel 1 (5)
10 = Channel 2 (6)
11 = Channel 3 (7)
Clear Byte Pointer — WO. No specific pattern. Command enabled with a write to the I/O port
address. Writing to this register initializes the byte pointer flip/flop to a known state. It clears the
internal latch used to address the upper or lower byte of the 16-bit Address and Word Count
Registers. The latch is also cleared by part reset and by the Master Clear command. This command
precedes the first access to a 16-bit DMA controller register. The first access to a 16-bit register will
then access the significant byte, and the second access automatically accesses the most significant
byte.
or Master Clear disables autoinitialization.
terminal count (TC).
Ch. #0
Ch. #4
0000 00xx
No
Ch. #0
Ch. #4
xxxx xxxx
No
–
–
–
–
3 = 0Bh;
7 = D6h
3 = 0Ch;
7 = D8h
Description
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
WO
8-bit
Core
WO
8-bit
Core
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