FW82801EB Intel, FW82801EB Datasheet - Page 108

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.4.1.9
5.4.1.10
5.4.1.11
5.4.1.12
108
Note: If the cycle is not claimed by any peripheral (and subsequently aborted), the ICH5 returns a value
Note: The ICH5 does not support LPC Bus Masters performing I/O cycles. LPC Bus Masters should only
Note: The Low Pin Count Interface Specification, Revision 1.1 defines the LPCPD# protocol where there
Note: The ICH5 cannot accept PCI write cycles from PCI-to-PCI bridges or devices with similar
LPC Power Management
Configuration and Intel
I/O Cycles
For I/O cycles targeting registers specified in the ICH5’s decode ranges, the ICH5 performs I/O
cycles as defined in the Low Pin Count Interface Specification, Revision 1.1. These are 8-bit
transfers. If the processor attempts a 16-bit or 32-bit transfer, the ICH5 breaks the cycle up into
multiple 8-bit transfers to consecutive I/O addresses.
of all 1s (FFh) to the processor. This is to maintain compatibility with ISA I/O cycles where pull-up
resistors would keep the bus high if no device responds.
Bus Master Cycles
The ICH5 supports Bus Master cycles and requests (using LDRQ#) as defined in the Low Pin
Count Interface Specification, Revision 1.1. The ICH5 has two LDRQ# inputs, and thus supports
two separate bus master devices. It uses the associated START fields for Bus Master 0 (0010b) or
Bus Master 1 (0011b).
perform memory read or memory write cycles.
LPCPD# Protocol
Same timings as for SUS_STAT#. Upon driving SUS_STAT# low, LPC peripherals drive LDRQ#
low or tri-state it. ICH5 shuts off the LDRQ# input buffers. After driving SUS_STAT# active, the
ICH5 drives LFRAME# low, and tri-states (or drive low) LAD[3:0].
is at least 30 µs from LPCPD# assertion to LRST# assertion. This specification explicitly states
that this protocol only applies to entry/exit of low power states which does not include
asynchronous reset events. The ICH5 asserts both SUS_STAT# (connects to LPCPD#) and
PCIRST# (connects to LRST#) at the same time when the core logic is reset (via CF9h, PWROK,
or SYS_RESET#, etc.). This is not inconsistent with the LPC LPCPD# protocol.
LPC I/F Decoders
To allow the I/O cycles and memory mapped cycles to go to the LPC interface, the ICH5 includes
several decoders. During configuration, the ICH5 must be programmed with the same decode
ranges as the peripheral. The decoders are programmed via the Device 31:Function 0 configuration
space.
characteristics (specifically those with a “Retry Read” feature which is enabled) to an LPC device
if there is an outstanding LPC read cycle towards the same PCI device or bridge. These cycles are
not part of normal system operation, but may be encountered as part of platform validation testing
using custom test fixtures.
Bus Master Device Mapping and START Fields
Bus Masters must have a unique START field. In the case of the ICH5 that supports 2 LPC bus
masters, it drives 0010 for the START field for grants to bus master #0 (requested via LDRQ0#)
and 0011 for grants to bus master #1 (requested via LDRQ1#.). Thus, no registers are needed to
configure the START fields for a particular bus master.
®
ICH5 Implications
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet