FW82801EB Intel, FW82801EB Datasheet - Page 512

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

EHCI Controller Registers (D29:F7)
13.2.14
512
Table 165. Debug Port Register Address Map
USB 2.0-Based Debug Port Register
The Debug port’s registers are located in the same memory area, defined by the Base Address
Register (BAR), as the standard EHCI registers. The base offset for the debug port registers (A0h)
is declared in the Debug Port Base Offset Capability Register at Configuration offset 5Ah. The
specific EHCI port that supports this debug capability is indicated by a 4-bit field (bits 20
the HCSPARAMS register of the EHCI controller. The address map of the Debug Port registers is
shown in
NOTES:
CNTL_STS—Control/Status Register
Offset:
Default Value:
1. All of these registers are implemented in the core well and reset by PCIRST#, EHC HCRESET, and a EHC
2. The hardware associated with this register provides no checks to ensure that software programs the interface
27:17
D3-to-D0 transition
correctly. How the hardware behaves when programmed illegally is undefined.
Bit
31
30
29
28
16
Offset
ACh
A0h
A4h
A8h
B0h
Table
Reserved
OWNER_CNT — R/W.
0 = Ownership of the debug port is NOT forced to the EHCI controller (Default)
1 = Ownership of the debug port is forced to the EHCI controller (i.e. immediately taken away from
Reserved
ENABLED_CNT — R/W.
0 = Software can clear this by writing a 0 to it. The hardware clears this bit for the same conditions
1 = Debug port is enabled for operation. Software can directly set this bit if the port is already
Reserved
DONE_STS — R/WC. Software can clear this by writing a 1 to it.
0 = Request not complete
1 = Set by hardware to indicate that the request is complete.
the companion Classic USB Host Controller) If the port was already owned by the EHCI
controller, then setting this bit has no effect. This bit overrides all of the ownership-related bits
in the standard EHCI registers.
where the Port Enable/Disable Change bit (in the PORTSC register) is set. (Default)
enabled in the associated PORTSC register (this is enforced by the hardware).
165.
DATABUF[3:0]
DATABUF[7:4]
.
A0h
0000h
CNTL_STS
Mnemonic
CONFIG
USBPID
Control/Status
USB PIDs
Data Buffer (Bytes 3:0)
Data Buffer (Bytes 7:4)
Configuration
Register Name
Intel
Description
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W, R/WC, RO, WO
32 bits
00007F01h
00000000h
00000000h
Default
0000h
00h
R/W, R/WC,
R/W, RO
RO, WO
–
23) in
Type
R/W
R/W
R/W