FW82801EB Intel, FW82801EB Datasheet - Page 397

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Bit
3
2
1
0
LEGACY_USB_EN — R/W.
0 = Disable
1 = Enables legacy USB circuit to cause SMI#.
BIOS_EN — R/W.
0 = Disable
1 = Enables the generation of SMI# when ACPI software writes a 1 to the GBL_RLS bit.
End of SMI (EOS) — R/W (special). This bit controls the arbitration of the SMI signal to the
processor. This bit must be set for the Intel
has been asserted previously.
0 = Once the ICH5 asserts SMI# low, the EOS bit is automatically cleared.
1 = When this bit is set to 1, SMI# signal will be deasserted for 4 PCI clocks before its assertion. In
NOTE: ICH5 is able to generate 1st SMI after reset even though EOS bit is not set. Subsequent
GBL_SMI_EN — R/W.
0 = No SMI# will be generated by ICH5. This bit is reset by a PCI reset event.
1 = Enables the generation of SMI# in the system upon any enabled SMI event.
the SMI handler, the processor should clear all pending SMIs (by servicing them and then
clearing their respective status bits), set the EOS bit, and exit SMM. This will allow the SMI
arbiter to re-assert SMI upon detection of an SMI event and the setting of a SMI status bit.
SMI require EOS bit is set.
®
Description
ICH5 to assert SMI# low to the processor after SMI#
LPC Interface Bridge Registers (D31:F0)
397