FW82801EB Intel, FW82801EB Datasheet - Page 227

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 102. Debug Port Behavior
82801EB ICH5 / 82801ER ICH5R Datasheet
Behavioral Rules
Table 102
bits in the associated Port Status and Control register.
1. In both modes 1 and 2, the Debug Port controller must check for software requested debug
2. If the debug port is enabled by the debug driver, and the standard host controller driver resets
3. If the standard host controller driver suspends the USB port, then USB debug transactions are
4. The ENABLED_CNT bit in the debug register space is independent of the similar port control
OWNER_CNT
transactions at least every 125 microseconds.
the USB port, USB debug transactions are held off for the duration of the reset and until after
the first SOF is sent.
held off for the duration of the suspend/resume sequence and until after the first SOF is sent.
bit in the associated Port Status and Control register.
0
1
1
1
1
1
1
1
shows the debug port behavior related to the state of bits in the debug registers as well as
ENABLED_CT
X
0
1
1
1
1
1
1
Enable
Port
X
X
0
0
1
1
1
1
Run /
Stop
X
X
0
1
0
0
1
1
Suspend
X
X
X
X
0
1
0
1
Debug port is not being used. Normal
operation.
Debug port is not being used. Normal
operation.
Debug port in Mode 1. SYNC
keepalives sent plus debug traffic
Debug port in Mode 2. SOF (and only
SOF) is sent as keepalive. Debug
traffic is also sent. Note that no other
normal traffic is sent out this port,
because the port is not enabled.
Illegal. Host controller driver should
never put controller into this state
(enabled, not running and not
suspended).
Port is suspended. No debug traffic
sent.
Debug port in Mode 2. Debug traffic is
interspersed with normal traffic.
Port is suspended. No debug traffic
sent.
Debug Port Behavior
Functional Description
227