FW82801EB Intel, FW82801EB Datasheet - Page 63

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

2.18
2.19
Intel
®
Table 20. AC-Link Signals
Table 21. General Purpose I/O Signals (Sheet 1 of 2)
82801EB ICH5 / 82801ER ICH5R Datasheet
AC-Link
NOTE: An integrated pull-down resistor on AC_BIT_CLK is enabled when either:
General Purpose I/O
GPIO[47:42]
GPIO[39:35]
GPIO[31:29]
GPIO[28:27]
AC_SDIN[2:0]
AC_BIT_CLK
AC_SDOUT
AC_SYNC
AC_RST#
GPIO49
GPIO48
GPIO41
GPIO40
GPIO34
GPIO33
GPIO32
GPIO26
GPIO25
GPIO24
GPIO23
GPIO22
GPIO21
Name
Name
- The ACLINK Shutoff bit in the AC’97 Global Control Register (See
- Both Function 5 and Function 6 of Device 31 are disabled.
Otherwise, the integrated pull-down resistor is disabled.
Type
N/A
N/A
N/A
N/A
OD
OD
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
Type
O
O
O
I
I
Fixed as Output only. Processor I/F power well. Can instead be used as
CPUPWRGD.
Fixed as Output only. Main power well. Can instead be used as GNT4#.
Not implemented.
Fixed as Input only. Main power well. Can be used instead as LDRQ1#.
Fixed as Input only. Main power well. Can be used instead as REQ4#.
Not implemented.
Can be input or output. Main power well. Not multiplexed.
Not implemented.
Can be input or output. Main power well. Not multiplexed.
Not implemented.
Can be input or output. Resume power well. Not multiplexed.
Not implemented.
Can be input or output. Resume power well. Not multiplexed.
Can be input or output. Resume power well.
Fixed as output only. Main power well.
Fixed as output only. Main power well.
Fixed as output only. Main power well.
AC ’97 Reset: Master hardware reset to external codec(s).
AC ’97 Sync: 48 kHz fixed rate sample sync to the codec(s).
AC ’97 Bit Clock: 12.288 MHz serial data clock generated by the external
Codec(s). This signal has an integrated pull-down resistor (see Note below).
AC ’97 Serial Data Out: Serial TDM data output to the codec(s).
NOTE: AC_SDOUT is sampled at the rising edge of PWROK as a functional
AC ’97 Serial Data In 2:0: Serial TDM data inputs from the three codecs.
strap. See
Section 2.21.1
Description
Description
for more details.
Section
15.2.8) is set to 1, or
Signal Description
63