FW82801EB Intel, FW82801EB Datasheet - Page 107

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

5.4.1.8
Intel
®
Figure 11. Typical Timing for LFRAME#
Figure 12. Abort Mechanism
82801EB ICH5 / 82801ER ICH5R Datasheet
In the case of multiple byte cycles (e.g., for memory and DMA cycles) an error SYNC terminates
the cycle. Therefore, if the ICH5 is transferring 4 bytes from a device, if the device returns the error
SYNC in the first byte, the other three bytes will not be transferred.
Upon recognizing the SYNC field indicating an error, the ICH5 treats this the same as IOCHK#
going active on the ISA bus.
LFRAME# Usage
Start of Cycle
For Memory, I/O, and DMA cycles, the ICH5 asserts LFRAME# for one clock at the beginning of
the cycle
Abort Mechanism
When performing an Abort, the ICH5 drives LFRAME# active for four, consecutive clocks. On the
fourth clock, it drives LAD[3:0] to 1111b.
The ICH5 performs an abort for the following cases (possible failure cases):
•
•
•
•
LFRAME#
LAD[3:0]
ICH5 starts a Memory, I/O, or DMA cycle, but no device drives a valid SYNC after four
consecutive clocks.
ICH5 starts a Memory, I/O, or DMA cycle, and the peripheral drives an invalid SYNC pattern.
A peripheral drives an illegal address when performing bus master cycles.
A peripheral drives an invalid value.
LFRAME#
LCLK
LAD[3:0]
LCLK
(Figure
11). During that clock, the ICH5 drives LAD[3:0] with the proper START field.
Start
Start
Clock
1
CYCTYPE
Dir & Size
CYCTYPE
Dir & Size
ADDR
ADDR
Clocks
1 - 8
TAR
Syncs causes
TAR
Clocks
Too many
Sync
2
timeout
Clocks
Sync
1 - n
Peripheral must
stop driving
Clocks
Data
2
Functional Description
TAR
Clocks
2
Chipset will
drive high
Start
Clock
1
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