FW82801EB Intel, FW82801EB Datasheet - Page 473

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 161. Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation
82801EB ICH5 / 82801ER ICH5R Datasheet
When the USB host controller is in Software Debug Mode (USBCMD Register bit 5=1), the single
stepping software debug operation is as follows:
To Enter Software Debug Mode:
In Software Debug mode, when the Run/Stop bit is set, the host controller starts. When a valid TD
is found, the Run/Stop bit is reset. When the TD is finished, the HCHalted bit in the USBSTS
register (bit 5) is set.
The SW Debug mode skips over inactive TDs and only halts after an active TD has been executed.
When the last active TD in a frame has been executed, the host controller waits until the next SOF
is sent and then fetches the first TD of the next frame before halting.
This HCHalted bit can also be used outside of Software Debug mode to indicate when the host
controller has detected the Run/Stop bit and has completed the current transaction. Outside of the
Software Debug mode, setting the Run/Stop bit to 0 always resets the SOF counter so that when the
Run/Stop bit is set the host controller starts over again from the frame list location pointed to by the
Frame List Index (see FRNUM Register description) rather than continuing where it stopped.
10. HCD sets Run/Stop bit to 1 to resume normal schedule execution.
1. HCD puts host controller in Stop state by setting the Run/Stop bit to 0.
2. HCD puts host controller in Debug Mode by setting the SWDBG bit to 1.
3. HCD sets up the correct command list and Start Of Frame value for starting point in the Frame
4. HCD sets Run/Stop bit to 1.
5. Host controller executes next active TD, sets Run/Stop bit to 0, and stops.
6. HCD reads the USBCMD register to check if the single step execution is completed
7. HCD checks results of TD execution. Go to step 4 to execute next TD or step 8 to end
8. HCD ends Software Debug mode by setting SWDBG bit to 0.
9. HCD sets up normal command list and Frame List table.
SWDBG
(Bit 5)
List Single Step Loop.
(HCHalted=1).
Software Debug mode.
0
0
1
1
Run/Stop
(Bit 0)
0
1
0
1
If executing a command, the host controller completes the command and then
stops. The 1.0 ms frame counter is reset and command list execution resumes
from start of frame using the frame list pointer selected by the current value in
the FRNUM register. (While Run/Stop=0, the FRNUM register can be
reprogrammed).
Execution of the command list resumes from Start Of Frame using the frame list
pointer selected by the current value in the FRNUM register. The host controller
remains running until the Run/Stop bit is cleared (by software or hardware).
If executing a command, the host controller completes the command and then
stops and the 1.0 ms frame counter is frozen at its current value. All status are
preserved. The host controller begins execution of the command list from where
it left off when the Run/Stop bit is set.
Execution of the command list resumes from where the previous execution
stopped. The Run/Stop bit is set to 0 by the host controller when a TD is being
fetched. This causes the host controller to stop again after the execution of the
TD (single step). When the host controller has completed execution, the HC
Halted bit in the Status Register is set.
Description
UHCI Controllers Registers
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