FW82801EB Intel, FW82801EB Datasheet - Page 507

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

13.2.11
13.2.12
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
CONFIGFLAG—Configure Flag Register
ASYNCLISTADDR—Current Asynchronous List Address
Register
Offset:
Default Value:
This 32-bit register contains the address of the next asynchronous queue head to be executed. Since
the ICH5 host controller operates in 64-bit mode (as indicated by a 1 in 64-bit Addressing
Capability field in the HCCPARAMS register), then the most significant 32 bits of every control
data structure address comes from the CTRLDSSEGMENT register. Bits [4:0] of this register
cannot be modified by system software and will always return 0s when read. The memory structure
referenced by this physical memory pointer is assumed to be 32-byte aligned.
Offset:
Default Value:
This 32-bit register contains the address of the next asynchronous queue head to be executed. Since
the ICH5 host controller operates in 64-bit mode (as indicated by a 1 in 64-bit Addressing
Capability field in the HCCPARAMS register), then the most significant 32 bits of every control
data structure address comes from the CTRLDSSEGMENT register. Bits [4:0] of this register
cannot be modified by system software and will always return 0s when read. The memory structure
referenced by this physical memory pointer is assumed to be 32-byte aligned.
31:5
31:1
Bit
4:0
Bit
0
Reserved. Read from this field will always return 0.
Link Pointer Low (LPL) — R/W. These bits correspond to memory address signals [31:5],
respectively. This field may only reference a Queue Head (QH).
Reserved. These bits are reserved and their value has no effect on operation.
Configure Flag (CF) — R/W. Host software sets this bit as the last action in its process of
configuring the Host Controller. This bit controls the default port-routing control logic. Bit values and
side-effects are listed below. See section 4 of the Enhanced Host Controller Interface Specification
for Universal Serial Bus, Revision 1.0 for operation details.
0 = Port routing control logic default-routes each port to the classic host controllers (default).
1 = Port routing control logic default-routes all ports to this host controller.
CAPLENGTH + 18
00000000h
CAPLENGTH + 40
00000000h
–
–
1Bh
43h
Description
Description
Attribute:
Size:
Attribute:
Size:
EHCI Controller Registers (D29:F7)
R/W
32 bits
R/W
32 bits
507