FW82801EB Intel, FW82801EB Datasheet - Page 91

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Cycle Completion: The LAN controller completes (terminates) its initiated memory burst cycles
in the following cases:
Memory Write and Invalidate
The LAN controller has four Direct Memory Access (DMA) channels. Of these four channels, the
Receive DMA is used to deposit the large number of data bytes received from the link into system
memory. The Receive DMA uses both the Memory Write (MW) and the Memory Write and
Invalidate (MWI) commands. To use MWI, the LAN controller must guarantee the following:
To ensure the above conditions, the LAN controller may use the MWI command only under the
following conditions:
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Normal Completion: All transaction data has been transferred to or from the target device
(for example, host main memory).
Backoff: Latency Timer has expired and the bus grant signal (GNT#) was removed from the
LAN controller by the arbiter, indicating that the LAN controller has been preempted by
another bus master.
Transmit or Receive DMA Maximum Byte Count: The LAN controller burst has reached
the length specified in the Transmit or Receive DMA Maximum Byte Count field in the
Configure command block.
Target Termination: The target may request to terminate the transaction with a target-
disconnect, target-retry, or target-abort. In the first two cases, the LAN controller initiates the
cycle again. In the case of a target-abort, the LAN controller sets the Received Target-Abort bit
in the PCI Configuration Status field (PCI Configuration Status register, bit 12) and does not
re-initiate the cycle.
Master Abort: The target of the transaction has not responded to the address initiated by the
LAN controller (in other words, DEVSEL# has not been asserted). The LAN controller simply
deasserts FRAME# and IRDY# as in the case of normal completion.
Error Condition: In the event of parity or any other system error detection, the LAN
controller completes its current initiated transaction. Any further action taken by the LAN
controller depends on the type of error and other conditions.
Minimum transfer of one cache line.
Active byte enable bits (or BE[3:0]# are all low) during MWI access.
The LAN controller may cross the cache line boundary only if it intends to transfer the next
cache line too.
The Cache Line Size (CLS) written in the CLS register during PCI configuration is 8 or 16
DWords.
The accessed address is cache line aligned.
The LAN controller has at least 8 or 16 DWords of data in its receive FIFO.
There are at least 8 or 16 DWords of data space left in the system memory buffer.
The MWI Enable bit in the PCI Configuration Command register, bit 4, should is set to 1b.
The MWI Enable bit in the LAN Controller Configure command should is set to 1b.
Functional Description
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