FW82801EB Intel, FW82801EB Datasheet - Page 529

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

14.2.14
14.2.15
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
Note: This register is in the resume well and is reset by RSMRST#.
Note: This register is in the resume well and is reset by RSMRST#.
SMBUS_PIN_CTL—SMBUS Pin Control Register
(SMBUS—D31:F3)
Register Offset:
Default Value:
SLV_STS—Slave Status Register
(SMBUS—D31:F3)
Register Offset:
Default Value:
All bits in this register are implemented in the 64 kHz clock domain. Therefore, software must poll
this register until a write takes effect before assuming that a write has completed internally.
Bit
7:3
Bit
7:1
2
1
0
0
Reserved
SMBCLK_CTL — R/W.
1 = The SMBCLK pin is not overdriven low. The other SMBus logic controls the state of the pin.
0 = Intel
SMBDATA_CUR_STS — RO. This read-only bit has a default value that is dependent on an
external signal level. This pin returns the value on the SMBDATA pin. This allows software to read
the current state of the pin.
0 = Low
1 = High
SMBCLK_CUR_STS — RO. This read-only bit has a default value that is dependent on an external
signal level. This pin returns the value on the SMBCLK pin. This allows software to read the current
state of the pin.
0 = Low
1 = High
Reserved
HOST_NOTIFY_STS — R/WC. The Intel
a successful Host Notify Command on the SMLink pins. Software reads this bit to determine that the
source of the interrupt or SMI# was the reception of the Host Notify Command. Software clears this
bit after reading any information needed from the Notify address and data registers by writing a 1 to
this bit. Note that the ICH5 will allow the Notify Address and Data registers to be over-written once
this bit has been cleared. When this bit is 1, the ICH5 will NACK the first byte (host address) of any
new “Host Notify” commands on the SMLink. Writing a 0 to this bit has no effect.
otherwise indicate for the SMBCLK pin. (Default)
®
ICH5 drives the SMBCLK pin low, independent of what the other SMB logic would
0Fh
See below
10h
00h
®
ICH5 sets this bit to a 1 when it has completely received
Description
Description
Attribute:
Size:
Attribute:
Size:
SMBus Controller Registers (D31:F3)
R/W, RO
8 bits
R/WC
8 bits
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