FW82801EB Intel, FW82801EB Datasheet - Page 410

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.12.1
9.12.2
410
GPIO_USE_SEL—GPIO Use Select Register
Offset Address:
Default Value:
Lockable:
GP_IO_SEL—GPIO Input/Output Select Register
Offset Address:
Default Value:
Lockable:
31:29, 26
23:21,
14:15,
11:9,
28:27
25:24
23:16
Bit
5:0
15:0
Bit
GPIO_USE_SEL[23:21, 15:14, 11:9, 5:0] — R/W. Each bit in this register enables the
corresponding GPIO (if it exists) to be used as a GPIO, rather than for the native function.
0 = Signal used as native function.
1 = Signal used as a GPIO.
NOTE: Bits 31:29, 26 are not implemented because there is no corresponding GPIO.
NOTE: Bits 28:27, 25, 13:12, and 8:7 are not implemented because the corresponding GPIOs are
NOTE: Bits 16:17 are not implemented because the GPIO selection is controlled by bits 0:1. The
After a full reset (RSMRST#) all multiplexed signals in the resume and core wells are configured as
their native function rather than as a GPIO. After just a PCIRST#, the GPIO in the core well are
configured as their native function.
Reserved
Always 0. The GPIOs are fixed as outputs.
Always 1. These GPIOs are fixed as inputs.
GPIO[n]_SEL — R/W.
0 = Output. The corresponding GPIO signal is an output.
1 = Input. The corresponding GPIO signal is an input.
not multiplexed.
REQ/GNT# pairs are enabled/disabled together. For example, if bit 0 is set to 1 then the
REQ/GNTA# pair will function as GPIO0 and GPIO16.
GPIOBASE + 00h
1A003180h
No
GPIOBASE +04h
0000FFFFh
No
Intel
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
32-bit
Core for 0:7 and 16:23
Resume for 8:15 and 24:31
R/W
32-bit
Resume