FW82801EB Intel, FW82801EB Datasheet - Page 99

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Transmit Command during Normal Operation
To serve a transmit request from the TCO controller, the ICH5 LAN controller first completes the
current transmit DMA, sets the TCO Request bit in the PMDR register (see
Section
7.2), and then
responds to the TCO controller’s transmit request. Following the completion of the TCO transmit
DMA, the LAN controller increments the Transmit TCO statistic counter (described in
Section
7.2.14). Following the completion of the transmit operation, the ICH5 increments the
nominal Transmit statistic counters, clears the TCO Request bit in the PMDR register, and resumes
its normal transmit flow. The receive flow is not affected during this entire period of time.
Receive TCO
The ICH5 LAN controller supports receive flow towards the TCO controller. The ICH5 can
transfer only TCO packets, or all packets that passed MAC address filtering according to its
configuration and mode of operation as detailed below. While configured to transfer only TCO
packets, it supports Ethernet type II packets with optional VLAN tagging.
Force TCO Mode: While the ICH5 is in the force TCO mode, it may receive packets (TCO or all)
directly from the TCO controller. Receiving TCO packets and filtering level is controlled by the set
Receive enable command from the TCO controller. Following a reception of a TCO packet, the
ICH5 increments its nominal Receive statistic counters as well as the Receive TCO counter.
Dx>0 Power State: While the ICH5 is in a powerdown state, it may receive TCO packets or all
directly to the TCO controller. Receiving TCO packets is enabled by the set Receive enable
command from the TCO controller. Although TCO packet might match one of the other wake up
filters, once it is transferred to the TCO controller, no further matching is searched for and PME is
not issued. While receive to TCO is not enabled, a TCO packet may cause a PME if configured to
do so (setting TCO to 1 in the filter type).
D0 Power State: At D0 power state, the ICH5 may transfer TCO packets to the TCO controller. At
this state, TCO packets are posted first to the host memory, then read by the ICH5, and then posted
back to the TCO controller. After the packet is posted to TCO, the receive memory structure (that is
occupied by the TCO packet) is reclaimed. Other than providing the necessary receive resources,
there is no required device driver intervention with this process. Eventually, the ICH5 increments
the receive TCO static counter, clears the TCO request bit, and resumes normal control.
Read ICH5 Status (PM and Link State)
The TCO controller is capable of reading the ICH5 power state and link status. Following a status
change, the ICH5 asserts LINKALERT# and then the TCO can read its new power state.
Set Force TCO Mode
The TCO controller put the ICH5 into the Force TCO mode. The ICH5 is set back to the nominal
operation following a PCIRST#. Following the transition from nominal mode to a TCO mode, the
ICH5 aborts transmission and reception and loses its memory structures. The TCO may configure
the ICH5 before it starts transmission and reception if required.
Note: The Force TCO is a destructive command. It causes the ICH5 to lose its memory structures, and
during the Force TCO mode the ICH5 ignores any PCI accesses. Therefore, it is highly
recommended to use this command by the TCO controller at system emergency only.
®
Intel
82801EB ICH5 / 82801ER ICH5R Datasheet
99