FW82801EB Intel, FW82801EB Datasheet - Page 424

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

IDE Controller Registers (D31:F1)
10.1.19
424
IDE_TIM — IDE Timing Register
(IDE—D31:F1)
Address Offset:
Default Value:
This register controls the timings driven on the IDE cable for PIO and 8237 style DMA transfers. It
also controls operation of the buffer for PIO transfers.
13:12
11:10
9:8
Bit
15
14
7
6
5
IDE Decode Enable (IDE) — R/W. This bit enables/disables the Primary or Secondary decode.
The IDE I/O Space Enable bit in the Command register must be set in order for this bit to have any
effect. Additionally, separate configuration bits are provided (in the IDE I/O Configuration register) to
individually disable the primary or secondary IDE interface signals, even if the IDE Decode Enable
bit is set.
0 = Disable
1 = Enables the Intel
This bit effects the IDE decode ranges for both legacy and native-Mode decoding. It also effects the
corresponding primary or secondary memory decode range for IDE Expansion.
Drive 1 Timing Register Enable (SITRE) — R/W.
0 = Use bits 13:12, 9:8 for both drive 0 and drive 1.
1 = Use bits 13:12, 9:8 for drive 0, and use the Slave IDE Timing register for drive 1.
IORDY Sample Point (ISP) — R/W. The setting of these bits determine the number of PCI clocks
between IDE IOR#/IOW# assertion and the first IORDY sample point.
00 = 5 clocks
01 = 4 clocks
10 = 3 clocks
11 = Reserved
Reserved
Recovery Time (RCT) — R/W. The setting of these bits determines the minimum number of PCI
clocks between the last IORDY sample point and the IOR#/IOW# strobe of the next cycle.
00 = 4 clocks
01 = 3 clocks
10 = 2 clocks
11 = 1 clock
Drive 1 DMA Timing Enable (DTE1) — R/W.
0 = Disable
1 = Enable the fast timing mode for DMA transfers only for this drive. PIO transfers to the IDE data
Drive 1 Prefetch/Posting Enable (PPE1) — R/W.
0 = Disable
1 = Enable Prefetch and posting to the IDE data port for this drive.
Drive 1 IORDY Sample Point Enable (IE1) — R/W.
0 = Disable IORDY sampling for this drive.
1 = Enable IORDY sampling for this drive.
170–177h for secondary) and Control Block (3F6h for primary and 376h for secondary).
port will run in compatible timing.
Primary:
Secondary: 42
0000h
®
ICH5 to decode the associated Command Blocks (1F0–1F7h for primary,
40
–
–
41h
43h
Intel
Description
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
16 bits