FW82801EB Intel, FW82801EB Datasheet - Page 454

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

SATA Controller Registers (D31:F2)
11.1.40
454
BFCS—BIST FIS Control/Status Register
(SATA–D31:F2)
Address Offset:
Default Value:
31:12
Bits
7:2
1:0
11
10
9
8
Reserved
BIST FIS Successful (BFS) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set any time a BIST FIS transmitted by Intel
NOTE: This bit must be cleared by software prior to initiating a BIST FIS.
BIST FIS Failed (BFF) — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set any time a BIST FIS transmitted by ICH5 receives an R_ERR completion status
NOTE: This bit must be cleared by software prior to initiating a BIST FIS.
Port 1 BIST FIS Initiate (P1BFI) — R/W. When a rising edge is detected on this bit field, the ICH5
initiates a BIST FIS to the device on Port 1, using the parameters specified in this register and the
data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 1 is
present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software
must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional
BIST FISes or to return the ICH5 to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P1BFI bit to initiate
another BIST FIS. This can be retried until the BIST FIS eventually completes successfully.
Port 0 BIST FIS Initiate (P0BFI) — R/W. When a rising edge is detected on this bit field, the ICH5
initiates a BIST FIS to the device on Port 0, using the parameters specified in this register and the
data specified in BFTD1 and BFTD2. The BIST FIS will only be initiated if a device on Port 0 is
present and ready (not partial/slumber state). After a BIST FIS is successfully completed, software
must disable and re-enable the port using the PxE bits at offset 92h prior to attempting additional
BIST FISes or to return the ICH5 to a normal operational mode. If the BIST FIS fails to complete, as
indicated by the BFF bit in the register, then software can clear then set the P0BFI bit to initiate
another BIST FIS. This can be retried until the BIST FIS eventually completes successfully.
BIST FIS Parameters. These 6 bits form the contents of the upper 6 bits of the BIST FIS Pattern
Definition in any BIST FIS transmitted by the ICH5. This field is not port specific — its contents will be
used for any BIST FIS initiated on port 0 on port 1. The specific bit definitions are:
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Reserved
status from the device.
from the device.
T – Far End Transmit mode
A – Align Bypass mode
S – Bypass Scrambling
L – Far End Retimed Loopback
F – Far End Analog Loopback
P – Primitive bit for use with Transmit mode
E0h
00000000h
–
E3h
Intel
Description
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
®
ICH5 receives an R_OK completion
R/W, R/WC
32 bits