FW82801EB Intel, FW82801EB Datasheet - Page 435

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

11.1.3
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
PCICMD—PCI Command Register
(SATA–D31:F2)
Address Offset:
Default Value:
15:11
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved
Interrupt Disable — R/W.
0 = Enables the SATA host controller to assert INTA# (native mode), IRQ14/15 (legacy mode), and
1 = The interrupt will be deasserted and it may not generate MSIs.
Fast Back to Back Enable (FBE) — RO. Reserved as 0.
SERR# Enable (SERR_EN) — RO. Reserved as 0.
Wait Cycle Control (WCC) — RO. Reserved as 0.
Parity Error Response (PER) — R/W.
0 = Disabled. SATA controller will not generate PERR# when a data parity error is detected.
1 = Enabled. SATA controller will generate PERR# when a data parity error is detected.
VGA Palette Snoop (VPS) — RO. Reserved as 0.
Postable Memory Write Enable (PMWE) — RO. Reserved as 0.
Special Cycle Enable (SCE) — RO. Reserved as 0.
Bus Master Enable (BME) — R/W. This bit controls the Intel
for IDE Bus Master transfers. This bit does not impact the generation of completions for split
transaction commands.
Memory Space Enable (MSE) — RO. The SATA controller does not contain memory space.
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disables access to the Legacy or Native IDE ports (both Primary and Secondary) as well as the
1 = Enable. Note that the Base Address register for the Bus Master registers should be
MSI (if MSI is enabled).
Bus Master I/O registers.
programmed before this bit is set.
04h
0000h
–
05h
Description
Attribute:
Size:
SATA Controller Registers (D31:F2)
®
RO, R/W
16 bits
ICH5’s ability to act as a PCI master
435