FW82801EB Intel, FW82801EB Datasheet - Page 86

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.2.1.1
86
Parallel Subsystem Overview
The parallel subsystem is broken down into several functional blocks: a PCI bus master interface, a
micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/
EEPROM/ interface. The parallel subsystem also interfaces to the FIFO subsystem, passing data
(such as transmit, receive, and configuration data) and command and status parameters between
these two blocks.
The PCI bus master interface provides a complete interface to the PCI bus and is compliant with
the PCI Local Bus Specification, Revision 2.3. The LAN controller provides 32 bits of addressing
and data, as well as the complete control interface to operate on the PCI bus. As a PCI target, it
follows the PCI configuration format which allows all accesses to the LAN controller to be
automatically mapped into free memory and I/O space upon initialization of a PCI system. For
processing of transmit and receive frames, the integrated LAN controller operates as a master on
the PCI bus, initiating zero wait-state transfers for accessing these data parameters.
The LAN controller control/status register block is part of the PCI target element. The control/
status register block consists of the following LAN controller internal control registers: System
Control Block (SCB), PORT, EEPROM Control and Management Data Interface (MDI) Control.
The micromachine is an embedded processing unit contained in the LAN controller that enables
Adaptive Technology. The micromachine accesses the LAN controller’s microcode ROM, working
its way through the opcodes (or instructions) contained in the ROM to perform its functions.
Parameters accessed from memory, such as pointers to data buffers, are also used by the
micromachine during the processing of transmit or receive frames by the LAN controller. A typical
micromachine function is to transfer a data buffer pointer field to the LAN controller’s DMA unit
for direct access to the data buffer. The micromachine is divided into two units, Receive Unit and
Command Unit which includes transmit functions. These two units operate independently and
concurrently. Control is switched between the two units according to the microcode instruction
flow. The independence of the Receive and Command units in the micromachine allows the LAN
controller to execute commands and receive incoming frames simultaneously, with no real-time
processor intervention.
The LAN controller contains an interface to an external serial EEPROM. The EEPROM is used to
store relevant information for a LAN connection such as node address, as well as board
manufacturing and configuration information. Both read and write accesses to the EEPROM are
supported by the LAN controller. Information on the EEPROM interface is detailed in
Section
5.2.3.
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet