FW82801EB Intel, FW82801EB Datasheet - Page 561

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

16.1.3
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
PCICMD—PCI Command Register
(Modem—D31:F6)
Address Offset:
Default Value:
Lockable:
PCICMD is a 16-bit control register. Refer to the PCI Local Bus Specification, Revision 2.3 for
complete details on each bit.
15:11
Bit
10
9
8
7
6
5
4
3
2
1
0
Reserved. Read 0.
Interrupt Disable (ID) — R/W.
0 = The INTx# signals may be asserted and MSIs may be generated.
1 = The AC ‘97 controller’s INTx# signal will be de-asserted and it may not generate MSIs.
Fast Back to Back Enable (FBE) — RO. Not implemented. Hardwired to 0.
SERR# Enable (SERR_EN) — RO. Not implemented. Hardwired to 0.
Wait Cycle Control (WCC) — RO. Not implemented. Hardwired to 0.
Parity Error Response (PER) — RO. Not implemented. Hardwired to 0.
VGA Palette Snoop (VPS) — RO. Not implemented. Hardwired to 0.
Memory Write and Invalidate Enable (MWIE) — RO. Not implemented. Hardwired to 0.
Special Cycle Enable (SCE) — RO. Not implemented. Hardwired to 0.
Bus Master Enable (BME) — R/W. This bit controls standard PCI bus mastering capabilities.
0 = Disable
1 = Enable
Memory Space Enable (MSE) — RO. Hardwired to 0, AC ‘97 does not respond to memory
accesses.
I/O Space Enable (IOSE) — R/W. This bit controls access to the I/O space registers.
0 = Disable access. (default = 0).
1 = Enable access to I/O space. The Native PCI Mode Base Address register should be
programmed prior to setting this bit.
04
0000h
No
–
05h
AC ’97 Modem Controller Registers (D31:F6)
Description
Attribute:
Size:
Power Well:
R/W, RO
16 bits
Core
561