FW82801EB Intel, FW82801EB Datasheet - Page 500

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

EHCI Controller Registers (D29:F7)
13.2.5
500
The second set at offsets 40h to the end of the implemented register space are implemented in the
Suspend power well. Unless otherwise noted, the suspend-well registers are reset by the assertion
of either of the following:
USB2.0_CMD—USB 2.0 Command Register
Offset:
Default Value:
•
•
31:24
23:16
15:8
11:8
Bit
7
6
5
4
Suspend well hardware reset
HCRESET
Reserved. These bits are reserved and should be set to 0 when writing this register.
Interrupt Threshold Control — R/W. System software uses this field to select the maximum rate at
which the host controller will issue interrupts. The only valid values are defined below. If software
writes an invalid value to this register, the results are undefined.
Value
00h
01h
02h
04h
08h
10h
20h
40h
Reserved. These bits are reserved and should be set to 0 when writing this register.
Unimplemented Asynchronous Park Mode Bits. Hardwired to 000b indicating the host controller
does not support this optional feature.
Light Host Controller Reset — RO. Hardwired to 0. The Intel
reset.
Interrupt on Async Advance Doorbell — R/W. This bit is used as a doorbell by software to tell the
host controller to issue an interrupt the next time it advances asynchronous schedule.
0 = The host controller sets this bit to a 0 after it has set the Interrupt on Async Advance status bit in
1 = Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all
NOTE: Software should not write a 1 to this bit when the asynchronous schedule is inactive. Doing
Asynchronous Schedule Enable — R/W. Default 0b. This bit controls whether the host controller
skips processing the Asynchronous Schedule.
0 = Do not process the Asynchronous Schedule
1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
Periodic Schedule Enable — R/W. Default 0b. This bit controls whether the host controller skips
processing the Periodic Schedule.
0 = Do not process the Periodic Schedule
1 = Use the PERIODICLISTBASE register to access the Periodic Schedule.
the USB2.0_STS register to a 1.
appropriate cached schedule state, it sets the Interrupt on Async Advance status bit in the
USB2.0_STS register. If the Interrupt on Async Advance Enable bit in the USB2.0_INTR
register is a 1 then the host controller will assert an interrupt at the next interrupt threshold. See
the Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 1.0 for
operational details.
so will yield undefined results.
1 micro-frame
2 micro-frames
4 micro-frames (default)
8 micro-frames (default, equates to 1 ms)
16 micro-frames (2 ms)
32 micro-frames (4 ms)
64 micro-frames (8 ms)
Maximum Interrupt Interval
Reserved
CAPLENGTH + 00
00080000h
–
03h
Description
Intel
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
®
ICH5 does not implement this optional
RW, RO
32 bits