FW82801EB Intel, FW82801EB Datasheet - Page 9

• Manufacturer Part Number: FW82801EB
• Manufacturer: Intel

Specifications of FW82801EB

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
5.14
5.15
5.16
5.13.6 Dynamic Processor Clock Control .......................................................................150
5.13.7 Sleep States ........................................................................................................151
5.13.8 Thermal Management..........................................................................................155
5.13.9 Event Input Signals and Their Usage ..................................................................156
5.13.10 ALT Access Mode................................................................................................159
5.13.11 System Power Supplies, Planes, and Signals .....................................................161
5.13.12 Clock Generators .................................................................................................163
5.13.13 Legacy Power Management Theory of Operation ...............................................164
System Management (D31:F0).........................................................................................164
5.14.1 Theory of Operation .............................................................................................165
5.14.2 Heartbeat and Event Reporting via SMBUS ........................................................166
General Purpose I/O .........................................................................................................170
5.15.1 GPIO Mapping .....................................................................................................170
5.15.2 Power Wells .........................................................................................................173
5.15.3 SMI# and SCI Routing .........................................................................................173
IDE Controller (D31:F1) ....................................................................................................174
5.16.1 PIO Transfers ......................................................................................................174
5.13.6.1 Throttling Using STPCLK#...................................................................151
5.13.6.2
5.13.7.1 Sleep State Overview ..........................................................................151
5.13.7.2 Initiating Sleep State ............................................................................152
5.13.7.3 Exiting Sleep States.............................................................................152
5.13.7.4 Sx-G3-Sx, Handling Power Failures ....................................................154
5.13.8.1 THRM# Signal......................................................................................155
5.13.8.2 THRM# Initiated Passive Cooling ........................................................155
5.13.8.3 THRM# Override Software Bit .............................................................155
5.13.8.4 Processor Initiated Passive Cooling
5.13.8.5 Active Cooling ......................................................................................156
5.13.9.1 PWRBTN# (Power Button) ..................................................................156
5.13.9.2 RI# (Ring Indicator)..............................................................................157
5.13.9.3 PME# (PCI Power Management Event) ..............................................158
5.13.9.4 SYS_RESET# Signal...........................................................................158
5.13.9.5 THRMTRIP# Signal .............................................................................158
5.13.10.1 Write Only Registers with Read Paths
5.13.10.2 PIC Reserved Bits................................................................................161
5.13.10.3 Read Only Registers with Write Paths
5.13.11.1 Power Plane Control with SLP_S3#,
5.13.11.2 SLP_S4# and Suspend-To-RAM Sequencing .....................................162
5.13.11.3 PWROK Signal ....................................................................................162
5.13.11.4 VRMPWRGD Signal ............................................................................162
5.13.11.5 Controlling Leakage and Power Consumption
5.13.13.1 APM Power Management ....................................................................164
5.14.1.1 Detecting a System Lockup .................................................................165
5.14.1.2 Handling an Intruder ............................................................................165
5.14.1.3 Detecting Improper Flash BIOS Programming ....................................165
5.14.1.4 Handling an ECC Error or Other Memory Error ...................................166
5.16.1.1 IDE Port Decode ..................................................................................174
(Via Programmed Duty Cycle on STPCLK#) .......................................156
in ALT Access Mode ............................................................................159
in ALT Access Mode ............................................................................161
SLP_S4# and SLP_S5#.......................................................................161
during Low-Power States.....................................................................163
Transition Rules among S0/Cx and Throttling States .........................151
Contents
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